Opcode |
Instruction |
Description |
|---|---|---|
|
66 0F C6 /r ib |
SHUFPD xmm1, xmm2/m128, imm8 |
Shuffle packed double-precision floating-point values selected by imm8 from xmm1 and xmm1/m128 to xmm1. |
Moves either of the two packed double-precision floating-point values from destination operand (first operand) into the low quadword of the destination operand; moves either of the two packed double-precision floating-point values in the source operand into to the high quadword of the destination operand (see Figure 3-16). The select operand (third operand) determines which values are moved to the destination operand.
The source operand can be an XXM register or a 128-bit memory location. The destination operand is an XMM register. The select operand is an 8-bit immediate: bit 0 selects which value is moved from the destination operand to the result (where 0 selects the low quadword and 1 selects the high quadword) and bit 1 selects which value is moved from the source operand to the result. Bits 3 through 7 of the shuffle operand are reserved.
IF SELECT.0 == 0
THEN DEST[63-0] 
DEST[63-0];
ELSE DEST[63-0] DEST[127-64]; FI;
IF SELECT.1 == 0
THEN DEST[127-64] SRC[63-0];
ELSE DEST[127-64] SRC[127-64]; FI;
SHUFPD __m128d _mm_shuffle_pd(__m128d a, __m128d b, unsigned int imm8)
None.
#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments If memory operand is not aligned on a 16-byte boundary, regardless of segment.
#SS(0) - For an illegal address in the SS segment.
#PF(fault-code) - For a page fault.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.
#GP(0) - If memory operand is not aligned on a 16-byte boundary, regardless of segment.
Interrupt 13 - If any part of the operand lies outside the effective address space from 0 to 0FFFFH.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.
Same exceptions as in Real Address Mode.
#PF(fault-code) - For a page fault.
For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.