Event ratio topicMemory Order Machine Clear Performance Impact

((Memory Order Machine Clear*500) / Clockticks)*100

As a general guide these numbers have been derived from experienced performance engineers:





A high value for this ratio indicates that the pipeline was cleared due to memory ordering issues, causing a negative impact on performance. This usually indicates false sharing. False sharing occurs when two threads access distinct or independent data that fall into the same cache line. The following cases can cause false sharing:

Advice: See Avoiding Memory Ordering Pipeline Clears