Tsuyoshi Iwagaki Assistant Professor
School of Information Science（Department of Information Science・Computer Systems and Networks）

■Degrees

B.E., Osaka Institute of Technology, Electronics Engineering (2000)
M.E., Nara Institute of Science and Technology, Information Science (2002)
Ph.D., Nara Institute of Science and Technology, In

■Professional Career

Classroom Assistant, Department of Electronic Engineering, Osaka Institute of Technology (1999-2000)
COE Research Fellow, Graduate School of Infomation Science, Nara Institute of Science and Technology (2003-2004)
Postdoctral Fellow, Graduate School of Infomation Science, Nara Institute of Science and Technology (2004-2005)
Associate, School of Infomation Science, Japan Advanced Institute of Science and Technology (2005-2007)
Assistant Professor, School of Infomation Science, Japan Advanced Institute of Science and Technology (2007-)

■Specialties

Design and Test of Digital Systems

■Research Keywords

Test Generation, Design for Testability, High Level Synthesis for Testability, Delay Fault

■Research Interests

Sequential Delay Test Generation Based on Circuit Pseudo Transformation
Sequential delay test generation is a very hard problem. In thisresearch, to accelerate sequential delay test generation, I considera class of easily delay testable sequential circuits and itstest generation model on the basis of the concept calledpseudo-circuit transformation.
Instruction-level Self-test for Processors
In recent years, instruction-level self-testing of processors getsa lot of attention as an alternative to scan testing. In thisresearch, I investigate an efficient method to generate testprograms for high-speed processors and study a design fortestability method that is oriented to instruction-levelself-testing.
Low Power Scan Testing
The excessive power consumption during scan testingcan degrade the reliability of a circuit under testand can cause faulted test results. In this research,I consider a test architecture and a test generationmethod to realize low power scan testing.
Non-scan Design for Delay Testability of Register Transfer Level Circuits
Scan design has some disadvantages (e.g., large hardware overhead,long test application time, inability to perform at-speed test,etc.) although it is widely used in industry. In this research,in order to overcome these disadvantages, I address a non-scandesign for delay testability for register transfer level circuits.

■Publications

◇Books

Book title: VLSI-SoC: research trends in VLSI and systems on chip: Contributed chapter title: Broadside transition test generation for partial scan circuits through stuck-at test generation;，Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara，Editors: G. De Micheli, S. Mir and R. Reis; Springer，2007，pp. 301-316

◇Published Papers

A pseudo-boolean technique for generating compact transition tests with all-output-propagation properties，Tsuyoshi Iwagaki and Mineo Kaneko，Proc. IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2010)，Jan. 2010
Safe clocking for the setup and hold timing constraints in datapath synthesis，Keisuke Inoue, Mineo Kaneko and Tsuyoshi Iwagaki，Proc. 19th ACM Great Lakes symposium on VLSI (GLSVLSI '09)，pp. 27-32，May 2009
Safe clocking based datapath synthesis for the setup and hold timing constraints，Keisuke Inoue, Mineo Kaneko and Tsuyoshi Iwagaki，第22回回路とシステム軽井沢ワークショップ，pp. 432-437，Apr. 2009

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■Extramural Activities

◇Academic Society Affiliations

23rd Workshop on Circuits and Systems in Karuizawa，Event Organizer，2009-2010
22nd Workshop on Circuits and Systems in Karuizawa，Organizer，2008-2009
Workshop on Circuits and Systems in Karuizawa，Program Committee Member，2006-