B.S., M.S. and Ph.D. from the University of Tokyo (1995, 1997, 2000) The University of Tokyo
2020 - : Japan Advanced Institute of Science and Technology , School of Information Science , Professor
2001 - 2020 : Japan Advanced Institute of Science and Technology , School of Information Science , Associate Professor
2001 - 2005 : Japan Science and Technology Agency, PRESTO Researcher
2000 - 2001 : Research Associate(JSPS) at the University of Tokyo
Computer systems
プロセッサアーキテクチャ, 並列計算機, リアルタイムシステム, 組込みシステム, 高機能アーキテクチャ
Parallel computer architecture
In parallel computer systems, dynamic reduction in messages is an effective scheme for preventing hot-spots which degrade performance. We study how to build a highly functional interconnection network that implements the reduction. Futher, we study adaptive directory scheme for management of shared data.
Memory system for large-scale data
We propose a reconfigurable cache memory that provides a buffer for large-scale data, and DMA mechanisms by a memory controller where stride data sequences are gathered and transferred efficiently. We evaluate the efficiency of them applied to real applications.
Embedded system architecture
We develop the RISC core for embedded systems which is configurable about the hardware elements according to demands on speed, size of hardware and consumption of electricity by various applications. Further, we develop real-time operating system which performs adaptive scheduling. In addition, we investigate reduction in electricity consumption for future architecture.
Processor Architecture for Real-Time Multitasking
A computer is used in multitasking fashion based on time sharing. In this rsearch, we propose the architecture that reduces the time required for switching processor contexts such as register contents and address space when an active task is switched, and alleviates constraints in scheduling of real-time applications.
Processor Design Laboratory, Enhanced Operating Systems, Operating Systems, Integrated Architecture, Digital Logic and Computer Design, Computer Architecture, Parallel and Distributed Systems Architecture
THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, IEEE Computer Society, ACM, INFORMATION PROCESSING SOCIETY OF JAPAN
Journal Senior Reviewer , Information Processing Society of Japan
Chief Examiner of Special Interest Group on Embedded Systems (SIGEMB) , Information Processing Society of Japan
Associate Editor of Editorial Committee of Special Issue of Embedded Systems Engineering in IPSJ Journal , Information Processing Society of Japan
・ Outstanding Paper Award , "Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)" , 2021
・ Best Paper Award , "IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2018)" , 2018
・ Best Paper Award , "International Conference on Information and Communication Technology for Embedded Systems" , 2017