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Mineo Kaneko Professor
School of Information Science、Security and Networks Area

■Degrees

B.E., M.E. and Ph.D. from Tokyo Institute of Technology (1981,1983,1986)

■Professional Career

Research Associate (1986), Lecturer (1988), Associate Professor (1992) at the Department of Electrical and Electronic Engineering, Tokyo Institute of Technology

■Specialties

Circuit theory and CAD for VLSIs, Fault Tolerant VLSI Computing, VLSI Signal Processing

■Research Keywords

Integrated circuits, Electronic circuits, Circuit theory, CAD, Optimization, Algorithm

■Research Interests

Circuit theory and CAD for VLSIs:
VLSI is a collection of a huge number of transistors and interconnections between them, and its design is to find one or some configurations which satisfy specifications in the functional behavior. Various kinds of performances associated with each configuration, such as area, speed, power and testability, are necessary also to be optimized. Hierarchical design is inevitably introduced to transform the problem to be computationally manageable. Hence, besides optimization algorithms, the design model for each abstract level, by which the final VLSI performance can be well estimated/controlled and at the same time the problem size can be reduced to be a manageable level, is also a key for successful CAD for VLSIs. An unified design model which covers from Boolean circuit level to transistor level and relevant optimization algorithms is one of the current topics. This approach aims to generate further optimized circuits than the previous approaches can achieve. High-level synthesis and S/H co-design are also included in our interests but they are discussed in the context of Fault tolerance or VLSI signal processing.
Fault tolerant VLSI computing:
Parallelism and pipelining together with the well structured multiple processing elements are promising solutions to various computation problems in the field. Fault-tolerance and dependability as well will become the important functions for WSI/VLSI systems. Multiple modular redundancy in mixed spatial-temporal space, algorithm based fault tolerance, reconfiguration and unified theory of these techniques are studied with emphasis on WSI/VLSI computation. We are also interested in High-level synthesis for application specified fault tolerant VLSI systems and related design theory and algorithms.
VLSI signal processing:
The evolution in VLSI technology allows various complicated and computationally intensive algorithms to be implemented on VLSI chip. Performance measures for such VLSI computation include function and performance of a computation algorithm itself, area(hardware cost), computation time, throughput rate, accuracy (finite word length effects), power, etc. We are trying to find solutions through an approach of the algorithm/software/hardware co-design. Modularity and regularity analysis of numerical computation algorithms, algorithm transformation and optimization and interaction between algorithm transformation and software/hardware co-design are the central interests of ours.

■Publications

◇Published Papers

  • Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing,Takayuki Moto, Mineo Kaneko,Proceedings of IEEE International Symposium on Circuits and Systems, 2018
  • Wire Congestion Aware High Level Synthesis Flow with Source Code Complier,Masato Tatsuoka, Mineo Kaneko,Proceedings of International Conference on IC Design and Technology, 2018,pp.101-104
  • Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability,Kazuho Katsumata, Junghoon Oh, Mineo Kaneko,Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies, 2018,pp.232-237

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◇Lectures and Presentations

  • 繰り返し分割再配置による2次元配置最適化手法,金子哲,高島康裕,佐藤真司,金子峰雄,電子情報通信学会 VLD研究会,2002.3
  • Assignment--Driven Heuristic Scheduling Based on Sensitivity to Iteration Period for Datapath Synthesis,Koji Oohashi, Mineo Kaneko,Design Gaia 2001,2001.11
  • Assignment--Driven Loop Pipelining and Its Application to High Level Synthesis,Toshiyuki Yorozuya, Koji Ohashi and Mineo Kaneko,Workshop on Synthesis and System Integration of Mixed Technology,2001.1

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■Extramural Activities

◇Academic Society Affiliations

  • The Association for Computing Machinery,1998-
  • The Institute of Electrical and Electronics Engineers,1990-
  • The Institute of Electronics, Information and Communication Engineers,1981-

◇Other Activities

  • Workshop on Synthesis and System Integration of Mixed Information Technologies,Publicity Co-Chair
  • Workshop on Synthesis and System Integration of Mixed Information Technologies,Local Arrangement Co-chair,2003/04/01 - 2004/10/31
  • Technical Group on VLSI design technologies,Member (1997-)

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■Academic Awards Received

  • Best Paper Award,IEICE,2012