北陸先端科学技術大学院大学 [JAIST] - 研究者総覧
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金子 峰雄 (カネコ ミネオ) 教授
情報科学系、セキュリティ・ネットワーク領域

185件中1-20件目

  • 1. Latency-Aware Selection of Check Variables for Soft-Error Tolerant Datapath Synthesis,Junghoon Oh, Mineo Kaneko,IEICE Trans. Foundations,Vol.E100-A,No.7,pp.1506-1510,July 2017
  • 2. KKT-Condition Inspired Solution of DVFS with Limited Number of Voltage Levels,Mineo Kaneko,Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS),pp.2400-2403,May 2017
  • 3. Margin Aware Timing Test and Tuning Algorithm for Post-Silicon Skew Tuning,Mineo Kaneko,Proceedings of the 60th IEEE Mid-West Symposium on Circuits and Systems,pp.1244-1247,August 2017
  • 4. マルチ・ドメイン・スキュー割り当てを考慮した資源割り当てとドメイン分割 (Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis),李 暁光, 金子峰雄 (Xiaoguang Li, Mineo Kaneko),電子情報通信学会VLSI設計技術研究会 (IEICE Technical Report on VLSI Design Technology), VLD2016-118,pp.85-90,March 2017
  • 5. 回路動作温度範囲に対する最適スキュー温度特性 (Optimum Temperature Dependent Timing Skew for Temperature Aware Design),曽我 慎, 金子峰雄 (Makoto Soga, Mineo Kaneko),電子情報通信学会VLSI設計技術研究会 (IEICE Technical Report on VLSI Design Technology), VLD2016-119,pp.91-96,March 2017
  • 6. スキュー調整を考慮した高位合成のMILP定式化 (MILP Approach to Skew-Aware High Level Synthesis,志村甲斐, 金子峰雄 (Kai Shimura, Mineo Kaneko),電子情報通信学会VLSI設計技術研究会 (IEICE Technical Report on VLSI Design Technology), VLD2016-120,pp.97-102,March 2017
  • 7. シミュレーテッド・アニーリングを利用した並列プレフィックス加算器の構成 (Optimization of Parallel Prefix Adder Using Simulated Annealing),本敬之, 金子峰雄 (Takayuki Moto, Mineo Kaneko),電子情報通信学会VLSI設計技術研究会 (IEICE Technical Report on VLSI Design Technology), VLD2016-127,pp.139-144,March 2017
  • 8. コンポーネント間近接制約に基づいた混合誤り訂正機構と回路面積評価 (Effect on the Chip Area of Component Adjacency Constraint for Soft-Error Tolerant Datapaths),呉 政訓, 金子峰雄 (Junghoon Oh, Mineo Kaneko),電子情報通信学会VLSI設計技術研究会 (IEICE Technical Report on VLSI Design Technology), VLD2016-129,pp.151-156,March 2017
  • 9. A Random Access Analog Memory with Master-Slave Structure for Implementing Hexadecimal Logic,Renyuan Zhang, Mineo Kaneko,IEEE International System-On-Chip Conference (SOCC) 2017,2017/9/
  • 10. LLVMベースの高位合成向けモデルのソース・コンパイラ:StoSを用いた高位合成フロー,立岡真人, 呉 政訓, 金子峰雄,情報処理学会DAシンポジウム,2017/8/
  • 11. Mixed Error Correction Scheme and Its Design Optimization for Soft-Error Tolerant Datapaths,Junghoon Oh, Mineo Kaneko,Proc. IEEE Asia Pacific Conference on Circuits and Systems,pp.362-365,October 2016
  • 12. KKT-Condition Based Study on DVFS for Heterogeneous Task Set,Mineo Kaneko,Proc. IEEE Asia Pacific Conference on Circuits and Systems,pp.717-720,October 2016
  • 13. Optimization of Temperature Dependent Intentional Skew for Temperature Aware Timing Design,Makoto Soga, Mineo Kaneko,Proceedings of 20th Workshop on Synthesis and System Integration of Mixed Information Technologies,pp.119-124,October 2016
  • 14. A Feasibility Study of Master-Slave Flipflop Design for Hexadecimal Logic,Renyuan Zhang, Mineo Kaneko,IEEE Industrial Electronics and Applications Conference,November 2016
  • 15. A 16-Valued Logic FPGA Architecture Employing Analog Memory Circuit,Renyuan Zhang, Mineo Kaneko,Proc. IEEE International Symposium on Circuits and Systems,pp.718-721,2016/5/
  • 16. Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing,Junghoon Oh, Mineo Kaneko,IEICE Trans. Fundations,Vol.E99-A,No.7,pp.1311-1322,2016/7/
  • 17. Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components,Junghoon Oh, Mineo Kaneko,IEEE Computer Society Annual Symposium on VLSI,pp.595-600,2016/7
  • 18. MILP-based Scheduling for Clock Latency Minimization in High-level Synthesis,Keisuke Inoue, Mineo Kaneko,Proc. 31st International Technical Conference on Circuits/Systems, Computers and Communications,pp.925-928,2016/7/
  • 19. 異種タスク集合に対する複数電圧レベルDVFSに関する一考察,金子峰雄,情報処理学会 DAシンポジウム論文集,pp.146-150,2016/9/
  • 20. Bitwidth-Aware Register Allocation and Binding for Clock Period Minimization,Keisuke Inoue, Mineo Kaneko,Proc. IEEE 58th International Midwest Symposium on Circuits and Systems,pp. 499-502,2015/08/

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