Mineo Kaneko Professor
School of Information Science（Department of Information Science・Computer Systems and Networks）

Results 1-20 of about 99

• 1.　Statistical Timing-Yield Driven Scheduling and FU Binding in Latch-Based Datapath Synthesis，Keisuke Inoue, Mineo Kaneko，Proceedings of IEEE Mid-West Symposium on Circuits and Systems，pp.631-634，2012/08/
• 2.　Timing-Test Scheduling for Constraint-Graph Based Post-Silicon Skew Tuning，Mineo Kaneko，Proceedings of IEEE International Conference on Computer Design，pp.460-465，2012/09/
• 3.　An Efficient Approach for Designing and Minimizing Reversible Programmable Logic Arrays，S. K. Mitra, L. Jamal, M. Kaneko, H. M. H. Babu，Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI)，pp.215-220，2012/5/
• 4.　Optimal Register-Type Selection during Resource Binding in Flip-Flop/Latch-Based High-Level Synthesis，Keisuke Inoue, Mineo Kaneko，Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI)，pp.79-82，2012/5/
• 5.　Post-Silicon Skew Tuning Algorithm Utilizing Setup and Hold Timing Tests，Mineo Kaneko, Li Jiang，Proceedings of IEEE International Symposium on Circuits and Systems，pp.125-128，2012/5/
• 6.　Register Binding and Domain Assignment for Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis，Keisuke Inoue, Mineo Kaneko，Proceedings of International Symposium on Quality Electronic Design (ISQED)，pp.778-783，2012/3/
• 7.　Performance-Driven Register Write Inhibition in High-Level Synthesis under Strict Maximum-Permissible Clock Latency Range，Keisuke Inoue, Mineo Kaneko，Proceedings of 17th Asia-South-Pacific Design Automation Conference (ASP-DAC 2012)，pp.239-244，2012/1/
• 8.　Reliable and Low-Power Clock Distribution Using Pre- and Post-Silicon Delay Adaptation in High-Level Synthesis，Keisuke Inoue, Mineo Kaneko，Proceedings of IEEE International Symposium on Circuits and Systems，pp.1664-1667，2012/5/
• 9.　A Basic Study on Timing-Test Scheduling for Post-Silicon Skew Tuning，Mineo Kaneko，電子情報通信学会 VLSI設計技術研究会 技術報告 VLD2011-79, DC2011-55，159-164，2011/11/
• 10.　On the NP-Hardness of Minimum-Period Register Binding，Keisuke Inoue, Mineo Kaneko，電子情報通信学会 基礎・境界ソサイエティ大会講演論文集，p.15，2011/9
• 11.　Early Planning for RT-Level Delay Insertion during Clock Skew-Aware Register Binding，Keisuke Inoue, Mineo Kaneko，Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration and System-on-Chip (VLSI-SoC)，pp.154-159，2011/10
• 12.　Operation Scheduling Considering Time Borrowing for High-Performance Latch-Based Circuits，Keisuke Inoue, Mineo Kaneko，Proceedins of 9th IEEE International NEW Circuits and System Conference，pp.245-248，2011/6
• 13.　Framework for Latch-Based High-Level Synthesis using Minimum-Delay Compensation，Keisuke Inoue, Mineo Kaneko，IPSJ Transactions on System LSI Design Methodology，Vol. 4，pp.232-244，2011/8
• 14.　Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis，Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki，IEICE Trans. Fundamentals, (April 2011)，Vol. E94-A，No. 4，pp.1067-1081，2011/4
• 15.　Ordered Coloring-Based Resource Binding for Datapaths with Improved Skew-Adjustability，Mineo Kaneko, Keisuke Inoue，Proceedings of ACM Geat Lakes Symposium on VLSI (GLSVLSI 2011), ACM Order , ISBN:978-1-4503-0667-6, (May 2011) (at Switzerland)，No. 477118，pp.307-312，2011/05
• 16.　Variable-Duty-Cycle Scheduling in Double-Edge-Triggered Flip-Flop-Based High-Level Synthesis，Keisuke Inoue, Mineo Kaneko，Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), (May 2011) (at Brazil)，pp.550-553，2011/05
• 17.　Flexible Test Scheduling for an Asynchronous On-chip Interconnect Through Special Data Transfer，Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko，IEICE Trans. Fundamentals，Vol. E94-A，No. 12，pp.2563-2570，2011/12/
• 18.　Register Binding and Domain Assignment for Multi-Domain Clock Skew Optimization，Keisuke Inoue, Mineo Kaneko，電子情報通信学会 VLSI設計技術研究会 技術報告 VLD2011-51，pp.61-66，2011/9
• 19.　A Complete Framework of Simultaneous Functional Unit and Register Binding with Skew Scheduling，Mineo Kaneko，Proceedings of International Symposium on Quality Electronic Design (ISQED), IEEE Catalog , ISBN: 978-1-61284-912-6, (March 2011) (at Santa Clara, CA, USA)，No. CFP11250-CDR，pp.189-195，2011/3
• 20.　Minimizing Clocking Patterns of Adjustable Safe Clocking for Timing Variation-Aware Datapaths，Keisuke Inoue, Mineo Kaneko，Proceedings of IEEE MidWest Symposium on Circuits And Systems, (August 2010)，pp. 113--116，2010/8

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