Professor Susumu Horiguchi

Susumu Horiguchi,
Graduate School of Information Science,
Japan Advanced Institute of Science and Technology,

NOTE: Japanese Page is here.
Email:hori@jaist.ac.jp
FAX:0761-51-1149
TEL:0761-51-1265(dial-in)

Professor Horiguchi joined with School of Information Science, JAIST in 1992. He received his Ph.D. in 1981 from Tohoku University. He was a faculty of Department of Information Science at Tohoku University from 1981 to 1992. He was a visiting scientist of IBM Thomas J. Watson Research Center from 1986 to 1987 and a visiting professor of The Center for Advanced Studies at the University of Southwestern Louisiana in 1994. He has been involved in organizing many international workshops, symposia and conference sponsored by IEEE, IEICE and IPS.

Research Interests

Our research interests are mainly concerned with massively parallel computer architectures and parallel algorithms, and multi-media systems.

1. Massively Parallel Computer Architectures
As a result of recent developments in VLSI technology, it is now possible to construct multiprocessor systems with thousands of processing elements. Various types of multiprocessor system are under intensive investigation in both industrial and university environments. This has created the need for research on parallel architectures and algorithms that can exploit the potentially high degree of parallelism in multiprocessor systems. We are studying hierarchical network architectures, hypercube multiprocessor systems, and multi-port memory computer architectures. e also are conducting research into principles of WSI/VLSI architectures by investigating reconfigurable architectures, hierarchical redundant architectures and interconnection networks for massively parallel systems.

2. Parallel Algorithms
Massively parallel machines with a large (greater than $10^6$) number of processing elements are promising means of satisfying the continuously increasing need for computing power in advance science and technology. We are interested hardware algorithms in systolic arrays and algorithms for massively parallel machines. We are studying parallel simulations, parallel computation models, parallel FFT algorithms, and memory-intensive computations for massively parallel systems. Our research focuses on high performance algorithms for real massively parallel computers.

3. Multi-Media Systems
Virtual Reality is a high-end user interface in which computer graphics is used to create a realistic looking world that responds to user inputs. We are studying recognition systems of manual alphabet and 3D-sculpture system using a hand gesture interface device. Other current research in multi-media is to create an automatic piano performance system that takes into account the performers' individualities.

Selected Publications

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    1. "Noisy Sort: A Memory-Intensive Sorting Algorithm", Linear Algebra and Its Application, Vol.115, pp.641-658 (1989).
    2. "Performance Evaluation of Parallel Fast Fourier Transform on a Multiprocessor Workstation", Journal of Parallel and Distributed Computing, Vol.12, pp.158-163 (1991).
    3. "Hybrid Systolic Sorters ", Parallel Computing, vol.17, No.9, pp.997-1007(1991).
    5. "Parallel Processing of Incremental Ray Tracing on a Shared-Memory Multiprocessor", The Visual Computer vol.9, pp.371-380 (1993).
    6. "Parallel 2-D FFT Algorithms on an Eight-Neighbor Processor Array", Trans. of IEE Japan, vol.114-C, No.5, pp.588-594 (1994).
    7. "Parallel FFT Algorithms Using Radix 4 Butterfly Computation on an Eight-Neighbor Processor Array", Parallel Computing vol.21, pp.121-136 (1995).
    8. "On the Multiple Bridge Fault Diagnosis of Baseline Multistage Interconnection Networks", IEICE Trans. Information and Systems Vol.E79-D, No.8, pp.1168-1179 (1996).
    9. "TESH: A New Hierarchical Interconnection Network for Massively Parallel Computing", IEICE Trans. Information and Systems,Vol.E80-D, No.9, pp.837-846 (1997)
    10. "VLSI Considerrations for TESH: A New Hierarchical Interconnection Network for 3-D Integration", IEEE Trans. VLSI Systems, Vol.6, No.3, pp.346-353 (1998)
    11. "Architecture, Defect Tolerance and Buffer Design for a New ATM Switch", IEEE Trans. on Components, Packaging, and Manufacturing Tech.-Part B, Vol.21, No.4, pp.338-345 (1998)

    International Conferences

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