Reconfigurable Computing Architecture,
Massively Parallel Computers,
Interconnection of Multiprocessor Systems,
Fault-Tolerant and Thermal Analysis of WSI stacks.
My research interests are mainly concerned with
reconfigurable computing architecture,
massively parallel computer architectures,
it's interconnection networks,
and implementation to 3D stacked wafers.
Ultra fine grade parallel processing by hard ware programming:
Logical circuits on a VLSI chip operate in parallel essentially
because sub-circuits on the chip execute their functions
independently. Thus, ultra fine graind parallel processing can be
achieved if operators in a software algorithm can be spread
as parallel arithmetic circuits on these VLSI chips.
In this research, a scheme is examined that extract operator
level parallelism from a software algorithm, compile them to
hardware description language (HDL),
and implement the algorithm as parallel arithmetic units
on hardware circuits, directly.
Interconnection networks for Massively Parallel Computer:
Multiprocessor systems consisting of millions of
processing elements have been expected
to solve advanced scientific and engineering problems
in the next decade.
Since the interconnection network is
one of the critical components of multiprocessor systems,
they are required network feature such as smaller diameter,
easy VLSI implementation, fault-tolerant schemes,
and good expandability.
We are studying hierarchical interconnection network named as
Shifted Recursive Torus (SRT) for scientific computing,
and discuss network performance, routing algorithms,
and fault-tolerant schemes.
Cooling Schemes for 3D Stacked Implementation:
For 3D Stacked Implementation systems,
cooling is one of the most crucial problems for implementation
massively parallel systems.
On the other hand,
the reconfiguration to avoid defects on wafers is also
important for wafer scale integration systems.
We are studying reconfiguration algorithms for
Shifted Recursive Torus (SRT) network in 3D stacked implementation
by considering thermo-radiation in stacked wafers implementation.
We discuss fault-tolerance schemes for SRT networks to keep
highly network performance in stacked wafers implementation.
Cooling approaches have been proposed for SRT
in stacked implementation.
Introducing a thermo-radiation model into SRT in
stacked implementation,
reconfiguration performance of SRT is evaluated.
Multi-port Memory Computer Architectures:
It is important for multiprocessor systems
to increase communication speed between processing elements.
We discuss a hypercube multiprocessor
based on a multiport memory which is able to
reduce the communication overhead.
A prototype multiprocessor system is constructed to evaluate
the communication performance of a multiport memory scheme.
It is confirmed that high communication performance is realized
by prototype system consisting of multiport memory.
Specialities: