INOGUCHI, Yasushi Professor
Information Science, Next-Generation Digital Infrastructure, Research Center for Advanced Computing Infrastructure
◆Degrees
B.E. degree from Tohoku University(1991), M.S. degree from JAIST(1994), Ph.D. degree from JAIST(1997) 東北大学
B.E. degree from Tohoku University(1991), M.S. degree from JAIST(1994), Ph.D. degree from JAIST(1997) 北陸先端科学技術大学院大学
◆Professional Experience
: 2008/4/1-2009/3/31University of South FloridaCourtesy Senior Research Scholar
: PRESTO, Japan Science and Technology Agency (2002-2006)
: Research Fellow of Japan Society for Promotion of Science (1994-1997)
◆Specialties
Information networks, Computer systems
◆Research Keywords
Massively Parallel, 並列処理, Reconfigurable System, e-Learning, Computer Architecture
◆Research Interests
Ultra fine grained parallel processing by hard ware programming
Logical circuits on a VLSI chip operate in parallel essentially because sub-circuits on the chip execute their functions independently. Thus, ultra fine grade parallel processing can be achieved if operators in a software algorithm can be spread as parallel arithmetic circuits on these VLSI chips.In this research, a scheme is examined that extract operator level parallelism from a software algorithm, compile them to hardware description language, and implement the algorithm as parallel arithmetic units on hardware circuits directly.



My research interests are mainly concerned with massively parallel computer architectures, it's interconnection networks, and implementation to 3D stacked wafers.
Interconnection networks for Massively Parallel Computer
Multiprocessor systems consisting of millions of processing elements have been expected to solve advanced scientific and engineering problems in the next decade. Since the interconnection network is one of the critical components of multiprocessor systems, they are required network feature such as smaller diameter, easy VLSI implementation, fault-tolerant schemes, and good expandability. We are studying hierarchical interconnection network named as Shifted Recursive Torus (SRT) for scientific computing, and discuss network performance, routing algorithms, and fault-tolerant schemes.
Cooling Schemes for 3D Stacked Implementation
For 3D Stacked Implementation systems, cooling is one of the most crucial problems to implement massively parallel systems. On the other hand, the reconfiguration to avoid defects on wafers is also important for wafer scale integration systems and some unused processing elements (PEs) are remained as a result of reconfiguration. Since operative PEs generate heavy heat but unused PEs generate no heat, we can cool the stacks replacing these PEs. We are studying reconfiguration algorithms for Shifted Recursive Torus (SRT) network in 3D stacked implementation by considering thermo-radiation in stacked wafers implementation. We discuss cooling schemes for SRT networks to keep highly cooling network performance in stacked wafers implementation. Cooling approaches have been proposed for SRT in stacked implementation. Introducing a thermo-radiation model into SRT in stacked implementation, cooling and reconfiguration performance of SRT is evaluated.
Multi-port Memory Computer Architectures
It is important for multiprocessor systems to increase communication speed between processing elements. We discuss a hypercube multiprocessor based on a multiport memory which is able to reduce the communication overhead. A prototype multiprocessor system is constructed to evaluate the communication performance of a multiport memory scheme. It is confirmed that high communication performance is realized by prototype system consisting of multiport memory.

■Publications

◆Published Papers
A Novel Cluster Prediction Approach Based on Locality-Sensitive Hashing for Fuzzy Clustering of Categorical Data.
Toan Nguyen Mau, Yasushi Inoguchi, Van-Nam Huynh
IEEE Access, 10, 34196-34206, 2022
A New Compression Scheme of Sparse Matrix Formats for Accurate Numerical Simulation on Site Environment with GPGPU
Tomoki Kawamura, Kazunori Yoneda, Takashi Iwamura, Masahiro Watanabe, Yasushi Inoguchi
情報処理学会論文誌数理モデル化と応用(TOM), 13, 2, 93-106, 2020
Locality-Sensitive Hashing for Information Retrieval System on Multiple GPGPU Devices
Toan Nguyen Mau, Yasushi Inoguchi
APPLIED SCIENCES-BASEL, 10, 7, -, 2020
SCCN: A Time-Effective Hierarchical Interconnection Network for Network-On-Chip
Mohammed N.M. Ali, M. M.Hafizur Rahman, Rizal Mohd Nor, Dhiren K. Behera, Tengku Mohd Tengku Sembok, Yasuyuki Miura, Yasushi Inoguchi
Mobile Networks and Applications, 24, 4, 1255-1264, 2019
A new container system constructed on JAIST facilities
宮下 夏苗, 間藤 真人, 本郷 研太, 井口 寧
大学情報システム環境研究 = Academic information processing environment research, 22, 11-20, 2019
◆Misc
Automatic Conversion from Snort PCRE to Verilog HDL
福田 真啓, 井口 寧
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 117, 377, 95-100, 2018
Performance Improvement on Music Fingerprint Searching from Large-Scale Database by Using Probabilistic Bias
福田 真啓, 井口 寧
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 115, 398, 167-172, 2016
北陸先端科学技術大学院大学 共有計算サーバ使用成果報告 2014
宮下 夏苗, 井口 寧
Technical memorandum, 2015, 1, 1-47, 2015
3P2-2 Reflective boundary condition with arbitrary boundary shape for compact explicit-finite difference time domain method(Poster Session)
Yamashita Osamu, Takao Tsuchiya, Iwaya Yukio, Otani Makoto, Inoguchi Yasushi
Proceedings of Symposium on Ultrasonic Electronics, 35, 0, 419-420, 2014
2P2-14 A Real-time Sound Rendering System based on the Finite-Difference Time-Domain Algorithm(Poster Session)
Yiyu Tan, Inoguchi Yasushi, Sato Yukinori, Otani Makoto, Iwaya Yukio, Matsuoka Hiroshi, Tsuchiya Takao
Proceedings of Symposium on Ultrasonic Electronics, 34, 235-236, 2013
◆Books
Computational Science and Its Applications -- ICCSA 2013, Lecture Notes in Computer Science, Hierarchical Tori Connected Mesh Network
共著, 197-210, Springer-Verlag Berlin Heidelberg, 2013
Hierarchical Interconnection Networks for Massively Parallel Computer Systems
共著, LAMBERT, 2011
Lecture Notes in Computer Science, Session 6A: Grid Scheduling and Algorithms II, Dynamic Task Scheduling Algorithm for Grid Computing System
共著, 578-583, Springer, 2005
北陸先端科学技術大学院大学 情報科学センター 利用の手引 (学内発行), 第3章 Convex
共著, 69-89 (Total 92 pages), JAIST Technical Memorandum, IS-TM-94-0002M, 1994
VMアプリケーションハンドブック, 第3章 サービス仮想計算機
共著, 65-109 (Total 514 pages), 共立出版, 1992
◆Conference Activities & Talks
Scalable Dynamic Locality-Sensitive Hashing for Structured Datase on Main Memory and GPGPU memory
10thInternational Conference on Grid Computing (GridCom-2018), Sydney, Australia, 2018
SnortのPCREからVerilog HDLへの自動変換
信学技法 RECONF2017-66, 慶應義塾大学 日吉キャンパス, 2018
Static Cost-Effective Analysis of a Shifted Completely Connected Network
International Conference on Computational Intelligence in Data Mining (ICCIDM 2017), Odisha, India, 2017
FPGAによる電子指紋検索の高速化事例
DAシンポジウム, 特別セッション: リコンフィギャラブルシステム~デバイス・設計環境・応用事例の最前線~, セッションオーガナイザー, 石川県 山代温泉, 2017
Probabilistic Strategies Based on Staged LSH for Speedup of Audio Fingerprint Searching with Ten Million Scale Database
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Bochum, DE, 2017

■Teaching Experience

Processor Design Laboratory, Parallel Processing, Computer Architecture, Digital Logic and Computer Design, プロセッサ設計演習, 並列処理, 計算機アーキテクチャ特論, 計算機構成とインタフェース

■Contributions to  Society

◆Academic Society Affiliations
サイエンティフィックシステム研究会, IEICE, Institute of Electrical and Electronics Engineers, Inc., The Institute of Electronics, Information and Communication Engineers, Information Processing Society Japan
◆Academic Contribution
17th Workshop on Advances in Parallel and Distributed Computational Models (APDCM 2014) , I am a member of Program Committee開催責任者所属・職・氏名: Oscar H. Ibarra, University of California, Santa Barbara , 2015 , Hyderabad, INDIA
IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips) XVIII , I am a member of Program Committee開催責任者所属・職・氏名: Tohoku Univ., Prof. H. Kobayashi , 2015 - 2015 , Yokohama, Japan
16th Workshop on Advances in Parallel and Distributed Computational Models (APDCM 2014) , プログラム委員 , 2014 , Phoenix, Arizona USA.