B.E. degree from Tohoku University(1991), M.S. degree from JAIST(1994), Ph.D. degree from JAIST(1997) 東北大学
B.E. degree from Tohoku University(1991), M.S. degree from JAIST(1994), Ph.D. degree from JAIST(1997) 北陸先端科学技術大学院大学
: 2008/4/1-2009/3/31University of South FloridaCourtesy Senior Research Scholar
: PRESTO, Japan Science and Technology Agency (2002-2006)
: Research Fellow of Japan Society for Promotion of Science (1994-1997)
Information networks, Computer systems
Massively Parallel, 並列処理, Reconfigurable System, e-Learning, Computer Architecture
Ultra fine grained parallel processing by hard ware programming
Logical circuits on a VLSI chip operate in parallel essentially because sub-circuits on the chip execute their functions independently. Thus, ultra fine grade parallel processing can be achieved if operators in a software algorithm can be spread as parallel arithmetic circuits on these VLSI chips.In this research, a scheme is examined that extract operator level parallelism from a software algorithm, compile them to hardware description language, and implement the algorithm as parallel arithmetic units on hardware circuits directly.
My research interests are mainly concerned with massively parallel computer architectures, it's interconnection networks, and implementation to 3D stacked wafers.
Interconnection networks for Massively Parallel Computer
Multiprocessor systems consisting of millions of processing elements have been expected to solve advanced scientific and engineering problems in the next decade. Since the interconnection network is one of the critical components of multiprocessor systems, they are required network feature such as smaller diameter, easy VLSI implementation, fault-tolerant schemes, and good expandability. We are studying hierarchical interconnection network named as Shifted Recursive Torus (SRT) for scientific computing, and discuss network performance, routing algorithms, and fault-tolerant schemes.
Cooling Schemes for 3D Stacked Implementation
For 3D Stacked Implementation systems, cooling is one of the most crucial problems to implement massively parallel systems. On the other hand, the reconfiguration to avoid defects on wafers is also important for wafer scale integration systems and some unused processing elements (PEs) are remained as a result of reconfiguration. Since operative PEs generate heavy heat but unused PEs generate no heat, we can cool the stacks replacing these PEs. We are studying reconfiguration algorithms for Shifted Recursive Torus (SRT) network in 3D stacked implementation by considering thermo-radiation in stacked wafers implementation. We discuss cooling schemes for SRT networks to keep highly cooling network performance in stacked wafers implementation. Cooling approaches have been proposed for SRT in stacked implementation. Introducing a thermo-radiation model into SRT in stacked implementation, cooling and reconfiguration performance of SRT is evaluated.
Multi-port Memory Computer Architectures
It is important for multiprocessor systems to increase communication speed between processing elements. We discuss a hypercube multiprocessor based on a multiport memory which is able to reduce the communication overhead. A prototype multiprocessor system is constructed to evaluate the communication performance of a multiport memory scheme. It is confirmed that high communication performance is realized by prototype system consisting of multiport memory.
Processor Design Laboratory, Parallel Processing, Computer Architecture, Digital Logic and Computer Design, プロセッサ設計演習, 並列処理, 計算機アーキテクチャ特論, 計算機構成とインタフェース
サイエンティフィックシステム研究会, IEICE, Institute of Electrical and Electronics Engineers, Inc., The Institute of Electronics, Information and Communication Engineers, Information Processing Society Japan
17th Workshop on Advances in Parallel and Distributed Computational Models (APDCM 2014) , I am a member of Program Committee開催責任者所属・職・氏名: Oscar H. Ibarra, University of California, Santa Barbara , 2015 , Hyderabad, INDIA
IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips) XVIII , I am a member of Program Committee開催責任者所属・職・氏名: Tohoku Univ., Prof. H. Kobayashi , 2015 - 2015 , Yokohama, Japan
16th Workshop on Advances in Parallel and Distributed Computational Models (APDCM 2014) , プログラム委員 , 2014 , Phoenix, Arizona USA.