iwa@hiroshima-cu

Research Areas †

Design and Test of Digital Systems

Publications †

Journal Papers †

1. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A test generation method for delay faults in sequential circuits with discontinuous reconvergence structure," Trans. of IEICE (DI), Vol. J86-D-I, No. 12, pp. 872-883, Dec. 2003. (In Japanese)
2. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A design scheme for delay testing of controllers using state transition information," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences (Special Section on VLSI Design and CAD Algorithms), Vol. E87-A, No. 12, pp. 3200-3207, Dec. 2004.
3. Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue and Hideo Fujiwara, "A low power deterministic test using scan chain disable technique," IEICE Trans. on Information and System, Vol. E89-D, No. 6, pp. 1931-1939, June 2006.

International Conferences †

1. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A path delay test generation method for sequential circuits based on reducibility to combinational test generation," Digest of Papers 8th IEEE European Test Workshop (ETW '03), pp. 307-312, May 2003.
2. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "An approach to non-scan design for delay fault testability of controllers," Digest of Papers 4th IEEE Workshop on RTL and High Level Testing (WRTLT '03), pp. 79-85, Nov. 2003.
3. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "Reducibility of sequential test generation to combinational test generation for several delay fault models," Proc. 12th IEEE Asian Test Symposium (ATS '03), pp. 58-63, Nov. 2003.
4. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A design methodology to realize delay testable controllers using state transition information," Proc. 9th IEEE European Test Symposium (ETS '04), pp. 168-173, May 2004.
5. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation," Proc. 10th IEEE European Test Symposium (ETS '05), pp. 48-53, May 2005.
6. Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue and Hideo Fujiwara, "A low power deterministic test using scan chain disable technique," Digest of Papers 6th IEEE Workshop on RTL and High Level Testing (WRTLT '05), pp. 184-191, July 2005.
7. Kazuko Kambe, Tsuyoshi Iwagaki, Michiko Inoue and Hideo Fujiwara, "Efficient constraint extraction for template-based processor self-test generation," Proc. 14th IEEE Asian Test Symposium (ATS '05), pp. 444-447, Dec. 2005.
8. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A new test generation model for broadside transition testing of partial scan circuits," Proc. 14th IFIP/IEEE/ACM International Conference on Very Large Scale Integration (VLSI-SoC '06), pp. 308-313, Oct. 2006.
9. Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko and Hideo Fujiwara, "Efficient path delay test generation based on stuck-at test generation using checker circuitry," Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD '07), pp. 418-423, Nov. 2007.
10. Tsuyoshi Iwagaki and Satoshi Ohtake, "Generation of power-constrained scan tests and its difficulty," Proc. IEEE International Design and Test Workshop, Dec. 2007. (To appear)

Technical Reports †

1. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A method of partially enhanced scan design for path delay faults based on discontinuous reconvergence structure," IEICE Technical Report (FTS2001-84), Vol. 101, No. 658, pp. 53-60, Feb. 2002. (In Japanese)
2. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A method of design for delay fault testability of controllers," IEICE Technical Report (DC2003-38), Vol. 103, No. 476, pp. 25-30, Nov. 2003.
3. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "Equivalence of sequential transition test generation and constrained combinational stuck-at test generation," IEICE Technical Report (DC2004-96), Vol. 104, No. 664, pp. 27-32, Feb. 2005.
4. Tsuyoshi Iwagaki, Satoshi Ohtake and Hideo Fujiwara, "A broadside test generation method for transition faults in partial scan circuits," IEICE Technical Report (DC2005-54), Vol. 105, No. 443, pp. 7-12, Dec. 2005.
5. Keisuke Inoue, Mineo Kaneko and Tsuyoshi Iwagaki, "A basic study on datapath synthesis considering delay variation," IEICE Technical Report (VLD2006-64), Vol. 106, No. 387, pp. 77-82, Nov. 2006. (In Japanese)
6. Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko and Hideo Fujiwara, "A test generation framework using checker circuits and its application to path delay test generation," IEICE Technical Report (CAS2006-76), Vol. 106, No. 512, pp. 37-42, Jan. 2007.

Professional Activities †

Program Committee Member of the Workshop on Circuits and Systems in Karuizawa
Member of IEEE
Member of IEICE
Member of IPSJ

Awards †

• Nov. 2004
  

  4th IEEE Workshop on RTL and High Level Testing Best Paper Award

• Feb. 2005
  

  IEEE Kansai Section Student Paper Award