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2024 年 †

  1. Yuya Ushioda, Mineo Kaneko, ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits, IEICE Transaction on Fundamentals, Vol.E107-A, No.3, pp.600-609, March 2024.
  2. Yuya Ushioda, Mineo Kaneko, Optimization of Pipeline Schedule for Hardware Efficient Two-Level Adiabatic Logic Circuits, The 25thWorkshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2024), 6 pages, 2024.
  3. 金子峰雄(Mineo Kaneko), タイミング調整性に優れたデータパス回路のための高位合成手法(High Level Dapapath Synthesis for Enhanced Timing Tunability), 電子情報通信学会VLSI 設計技術研究会技術報告(IEICE Technical Report on VLSI Design Technology), VLD2023-101, HWS2023-61, ICD2023-90, pp.12-17, 2024.
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2023 年 †

  1. 潮田裕也(Yuya Ushioda), 金子峰雄(Mineo Kaneko), 整数線形計画法による２LAL 型断熱論理回路の論理演算パイプライン最適化(Optimization of Pipelining and Decompute-Insertion for Hardware Efficient Two-Level Adiabatic Logic), 情報処理学会DA シンポジウム(IPSJ, Design Automation Symposium), DAS2023, 2023.
  2. Saher Javaid, Mineo Kaneko, Yasuo Tan, ''A Novel Energy Balancing Considering Periodic Behavior Pattern of Power System'', 58th International Universities Power Engineering Conference, 6 pages, 2023.
  3. Saher Javaid, Mineo Kaneko, Yasuo Tan, ''Supply-Dominated Energy Balancing for Periodic Operation of Power System'', Proceedings of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2 pages, 2023.
  4. Akanit Kwangkaew, Siriya Skolthanarat, Chalie Charoenlarpnopparut, Mineo Kaneko, Optimal Location and Sizing of Renewable Distributed Generators forImproving Robust Voltage Stability against Unconstrollable Reactive Compensation, IEEE Access, Vol. 11, pp. 52260-52274, DOI 10.1109/ACCESS.2023.3279716, 2023.
  5. Saher Javaid, Mineo Kaneko, Yasuo Tan, A Case Study on Robust Power/Energy Blancing Driven Cost Optimization for Sizing Energy Storage, Power Generators and Consumers, IEEE 6th International Conference on Energy Conservation and Efficiency, March 2023.
  6. Mineo Kaneko, Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders, Proceedings of IEEE International Symposium on Circuits and Systems, 5 pages, May 2023.
  7. 金子峰雄(Mineo Kaneko), 資源割当と遅延量分布の関係を考慮したスキュー調整型高位合成 (Skew Tunability Aware High Level Synthesis Considering Resource Binding-Driven Thermal Distribution), 電子情報通信学会 VLSI設計技術研究会 技術報告(IEICE Technical Report on VLSI Design Technology), VLD2022-89, HWS2022-60, pp. 97-102, 2023.
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2022 年 †

  1. Yuya Ushioda, Mineo Kaneko, Hardware Minimization of Two-Level Adiabatic Logic Based on Weighted Maximum Stable Set Problem, Proceedings of 2022 IEEE 40th International Conference on Computer Design (ICCD 2022), pp.394-397, 2022.
  2. 金子峰雄(Mineo Kaneko), 並列プレフィックス加算器の構造・桁並び同時最適化に関する考察 (A Study on Co-Optimization of Logical Structure and Bit-line Placement for Parallel Prefix Adders), 電子情報通信学会 VLSI設計技術研究会 技術報告 (IEICE Technical Report on VLSI Design Technology), VLD2022-20, pp.7-12, 2022.
  3. Kazuya Uryu, Mineo Kaneko, Co-optimization of Prefix Structure and Bit-Line Arrangement for Long Bit-Length Parallel Prefix Adders, Proceedings of The 24th Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI 2022) , pp.83-84, 2022.
  4. 潮田裕也(Yuya Ushioda), 金子峰雄(Mineo Kaneko), 最大安定集合問題に基づく断熱論理回路の回路規模縮小 (An Approach to Hardware Reduction in Adiabatic Logic Circuit based on Maximum Stable Set Problem), 情報処理学会 DAシンポジウム (IPSJ, Design Automation Symposium), DAS2022, pp.234-241, 2022.
  5. Tomohiro Noguchi, Omran Hindawi, Mineo Kaneko, Three-Dimensional Flexible-Module Placement for Stacked Three-Dimensional Integration, Proceedings of 2022 IEEE International Symposium on Circuits and Systems, pp.3260-3264, 2022.
  6. Saher Javaid, Mineo Kaneko, Yasuo Tan, LP-based Co-optimization of Power Generators and Power Storage Systems under the Condition of Safe Operation, IEEE ICCE-TW, 2022.
  7. 金子峰雄(Mineo Kaneko), 温度依存タイミングスキューを考慮したデータパス高位合成手法 (Datapath Synthesis Considering Temperature Dependent Timing Skew), 電子情報通信学会 VLSI設計技術研究会 技術報告 (IEICE Technical Report on VLSI Design Technology), VLD2021-79, HWS2021-56, pp.19-24, 2022-03.
  8. Akanit Kwangkaew, Saher Javaid, Chalie Charoenlarpnopparul, Mineo Kaneko, Optimal Location and Sizing of Renewable Distributed Generators Improving Voltage Stability and Security consiering Reactive Power Compensation, MDPI Energies, Volume 15, Issue 6, Article 2126, 23 pages, March 2022.
  9. Saher Javaid, Mineo Kaneko, Yasuo Tan, System Condition for Power Balancing between Fluctuating and Controllable Devices and Optimizing Storage Sizes, MDPI Energies, Vol.15, Article 1055, 2022.
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2021 年 †

  1. Saher Javaid, Mineo Kaneko, Yasuo Tan, Safe Operation Conditions of Electrical Power System Considering Power Balanceability among Power Generators, Loads, and Storage Devices, MDPI Energies, Vol.14, Article 4460, 27 pages, 2021.
  2. Saher Javaid, Mineo Kaneko, Yasuo Tan, Storage Minimization Considering System Conditions of Power Flow System, IEEE ICCE-Taiwan, 2021.
  3. Mineo Kaneko, ''Minimum Structural Transformation in Parallel Prefix Adders and Its Application to Search-Based Optimization'', IEEE International Symposium on Circuits and Systems (ISCAS 2021), 5 pages, 2021.
  4. Aye Myat Mon, Mineo Kaneko, Structural Doubling Operations for Efficient Design of Long Bit Length Parallel Prefix Adders, The 23d Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI), 2021.
  5. 金子峰雄(Mineo Kaneko), ばらつきと戦う集積回路設計ー仕掛けと最適化ー (Fighting Against Variations for High Performance LSI: Mechanisms and Optimization), '''電子情報通信学会 回路とシステム研究会 技術報告 (IEICE Technical Report on Circuits and Systems)''', CAS2020-76, CS2020-83, pp.23-28, 2021-03.
  6. 野口智博(Tomohiro Noguchi), Hindawi Omuran, 金子峰雄(Mineo Kaneko), 階層型３次元LSIのための３次元モジュール配置の一手法 (A Fundamental Study on Three-Dimensional Module Placement for Layered Three-Dimensional LSI), 電子情報通信学会 VLSI設計技術研究会 技術報告 (IEICE Technical Report on VLSI Design Technology), VLD2020-81, HW2020-56, pp.73-78, 2021-03.
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2020 年 †

  1. Masato Tatsuoka, Mineo Kaneko, High Level Congestion Detection from C/C++ Source Code for High Level Synthesis, IEICE Trans. Foundations, Vol. E103-A, No. 12, pp.1437-1446, December 2020.
  2. Saher Javaid, Mineo Kaneko, Yasuo Tan, An Efficient Testing Scheme for Power-Balanceability of Power System Including Controllable and Fluctuating Power Devices, MDPI Designs, Vol. 4, Issue 4, Article 48 (23 pages) December 2020.
  3. Mineo Kaneko, Insertion-Based Procedural Construction and Optimization of Parallel Prefix Adders, Proceedings of International Symposium on Circuits and Systems (ISCAS), Paper ID 1967, five pages, October 2020 (originally May 2020).
  4. Saher Javaid, Mineo Kaneko, Yasuo Tan, System Condition for Controllable Power Flow Sysem Considering Reaction Delay, IEEE International Conference on Consumer Electronics-Taiwan, 2020.
  5. Akanit Kwangkaew, Saher Javaid, Mineo Kaneko, Chalie Charoenlarpnopparut, A New Approach to Renewable Energy Sources Allocation Considering Robustness against Fluctuations, Proceedings of International Conference on Smart Grids and Energy Systems (SGES), pp.396-401, 2020.
  6. Saher Javaid, Mineo Kaneko, Tasuo Tan, Yuto Lim, Power Flow Management: A Review of Models and Issues, IEICE Technical Report on Information Networks, IN2019-82, pp.37-41, 2020-3.
  7. Saher Javaid, Mineo Kaneko, Yasuo Tan, Structural Condition for Controllable Power Flow System Containing Controllable and Fluctuating Power Devices, Section of Smart Grids and Microgrids, Energies, MDPI, Vol.13, No.1627; doi:10.3390/en13071627, 20 pages, April 2020.
  8. Mineo Kaneko, Two-Graph Approach to Temperature Dependent Skew Scheduling, Proceedings of International Symposium on Quality Electronic Design (ISQED), pp.432-437, March 2020.
  9. 金子峰雄(Mineo Kaneko), ２グラフ制約表現による温度依存クロック・スキュー・スケジュール (Thermal-Aware Clock Skew Scheduling Based on Two-Graph Approach), 電子情報通信学会 VLSI設計技術研究会 技術報告 (IEICE Technical Report on VLSI Design Technology), VLD2019-104, HWS2019-77, pp.59-64, March 2020.
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2019 年 †

  1. Saher Javaid, Mineo Kaneko, Yasuo Tan, Robustness Test Method of Power Flow System Containing Controllable and Fluctuating Power Devices, 11th IEEE Asia-Pacific Power and Energy Engineering Conference, December 2019.
  2. Saher Javaid, Mineo Kaneko, Yasuo Tan, Power Flow Management: Solvability Condition for a System with Controllable and Fluctuating Devices, 11th IEEE Asia-Pacific Power and Energy Engineering Conference, December 2019.
  3. Yuta Hiyama, Takayuki Todokoro, Kenshu Seto, Masato Tatsuoka, Yoshihito Nishida, Mineo Kaneko, High-Level Synthesis Code Optimization with Loop Fusion based on LLVM/Polly, The 22nd Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI 2019), pp.208-213, October 2019.
  4. Bo-Yu Tseng, Mineo Kaneko, Insertion Based Procedural Construction of Parallel Prefix Adders, The 22nd Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI 2019), pp.83-88, October 2019. (Outstanding Paper Award)
  5. Saher Javaid, Mineo Kaneko, Yasuo Tan, A Linear Programming Model for Power Flow Control Problem Considering Controllable and Fluctuating Power Devices, 2019 IEEE 8th Global Conference on Consumer Electronics, October 2019.
  6. Saher Javaid, Mineo Kaneko, Yasuo Tan, Power Flow Management for Smart Grids: Considering Renewable Energy and Demand Uncertainty, 2019 IEEE International Conference on Consumer Electronics -- Taiwan (IEEE ICCE-TW), two-pages, May 2019.
  7. Mineo Kaneko, A Novel Framework for Procedural Construction of Parallel Prefix Adders, Proceedings of 2019 IEEE International Symposium on Circuits and Systems, five pages, May 2019.
  8. 金子峰雄(Mineo Kaneko), 手続き的構成における挿入操作の多様性に基づく並列プレフィックス加算器の最適化 (Optimization of Parallel Prefix Adder Structure Generated by Insertion Operations, 電子情報通信学会 回路とシステム研究会 技術報告 (IEICE Technical Report on Circuits and Systems), CAS2019-48, pp.21-26, 2019.
  9. 金子峰雄(Mineo Kaneko), 挿入操作に基づく並列プレフィックス加算器の手続き的構成 (Procedural Construction of Parallel Prefix Adder by Insertion Operation), 情報処理学会DAシンポジウム (DA Symbosium 2019, IPSJ), pp.136-141, 2019.
  10. Mineo Kaneko, Timing Correction by Constrained Temperature Dependent Clock Skew, IEICE Technical Report on VLSI Design Technology, VLD2018-2013, HWS2018-66, pp.61-66, 2019.
  11. 立岡真人(Masato Tatsuoka), 金子峰雄(Mineo Kaneko), PDGのパターンマッチングに基づく高位合成入力コードからの配線混雑検出 (Pattern Matching Based Detection of Wire Congestion from Source Code Description for High Level Synthesis), 電子情報通信学会VLSI設計技術研究会 (IEICE Technical Report on VLSI Design Technology), VLD2018-96, HWS2018-59, pp.19-24, 2019.
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2018 年 †

  1. 金子峰雄(Mineo Kaneko), 並列プレフィックス加算器の手続き的構造生成(Procedural Construction of Parallel Prefix Adder), 情報処理学会DAシンポジウム (DA Symbosium 2018, IPSJ), pp.197-202, 2018.
  2. Masato Tatsuoka, Mineo Kaneko, Wire Congestion Aware High Level Synthesis Flow with Source Code Complier,'' Proceedings of IEEE International Conference on IC Design and Technology, pp.101-104, June 2018.
  3. Takayuki Moto, Mineo Kaneko, Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing, Proceedings of IEEE International Symposium on Circuits and Systems, five pages, May 2018.
  4. Kazuho Katsumata, Junghoon Oh, Mineo Kaneko, Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability, Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2018), pp.232-237, 2018.
  5. 西岡達紘, 金子峰雄 (Tatsuhiro Nishioka, Mineo Kaneko), バッファ挿入を考慮した並列プレフィックス加算器の最適化設計(Design Optimization of Parallel Prefix Adder Considering Buffer Insertion), 電子情報通信学会VLSI設計技術研究会 (IEICE Technical Report on VLSI Design Technology), VLD2017-109, pp.121-126, 2018.
  6. 呉政訓, 金子峰雄 (Junghoon Oh, Mineo Kaneko), コンポーネント間近接制約に基づいた混合誤り訂正機構の信頼性評価 (Reliability Evaluation of Mixed Error Correction Scheme for Soft-Error Tolerant Datapaths), 電子情報通信学会VLSI設計技術研究会 (IEICE Technical Report on VLSI Design Technology), VLD2017-102, pp.79-84, 2018.
  7. 馬(金成), 金子峰雄 (Cheng Ma, Mineo Kaneko), 耐故障FPGAのための一再構成手法とその評価(Reconfiguration for Fault Tolerant FPGA Considering Incremental Multiple Faults), 電子情報通信学会VLSI設計技術研究会 (IEICE Technical Report on VLSI Design Technology), VLD2017-101, pp.73-78, 2018.
  8. 立岡真人, 金子峰雄 (Masato Tatsuoka, Mineo Kaneko), ソース・コンパイラを用いた配線混雑改善の高位設計フロー(Congestion Aware High Level Synthesis Design Flow with Source Compiler), 電子情報通信学会VLSI設計技術研究会 (IEICE Technical Report on VLSI Design Technology), VLD2017-96, pp.43-48, 2018.
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2017 年 †

  1. Mineo Kaneko, A General Model of Timing Correction by Temperature Dependent Clock Skew, IEICE Technical Report on VLSI Design Technology, VLD2017-57, DC2017-63, pp.183-188, November 2017.
  2. 立岡真人, 呉 政訓, 金子峰雄 (Masato Tatsuoka, Junghoon Oh, Mineo Kaneko), LLVMベースの高位合成向けモデルのソース・コンパイラ：StoSを用いた高位合成フロー(High Level Synthesis Design Flow with Source Compiler Based on LLVM), 情報処理学会DAシンポジウム (DA Symbosium 2017, IPSJ), August 2017.
  3. Renyuan Zhang, Mineo Kaneko,A Random Access Analog Memory with Master-Slave Structure for Implementing Hexadecimal Logic, IEEE International System-On-Chip Conference (SOCC) 2017, pp.7-11, 2017.
  4. Mineo Kaneko,Margin Aware Timing Test and Tuning Algorithm for Post-Silicon Skew Tuning, '''2017 IEEE 60th International Widwest Symposium on Circuits and Systems (MWSCAS 2017)''', pp.1244-1247, August, 2017.
  5. Junghoon Oh, Mineo Kaneko,Latency-Aware Selection of Check Variables for Soft-Error Tolerant Datapath Synthesis, IEICE Trans. Foundations, Vol.E100-A, No.7, pp.1506-1510, July 2017.
  6. Mineo Kaneko, KKT-Condition Inspired Solution of DVFS with Limited Number of Voltage Levels, Proceedings of International Symposium on Circuits and Systems (ISCAS) 2017, pp.2400-2403, May, 2017.
  7. 李 暁光, 金子峰雄, マルチ・ドメイン・スキュー割り当てを考慮した資源割り当てとドメイン分割, 電子情報通信学会VLSI設計技術研究会, VLD2016-118, pp.85-90 March 2017.
  8. 曽我 慎, 金子峰雄, 回路動作温度範囲に対する最適スキュー温度特性, 電子情報通信学会VLSI設計技術研究会, VLD2016-119, pp.91-96 March 2017.
  9. 志村甲斐, 金子峰雄, スキュー調整を考慮した高位合成のMILP定式化, 電子情報通信学会VLSI設計技術研究会, VLD2016-120, pp.97-102 March 2017.
  10. 本敬之, 金子峰雄, シミュレーテッド・アニーリングを利用した並列プレフィックス加算器の構成, 電子情報通信学会VLSI設計技術研究会, VLD2016-127, pp.139-144 March 2017.
  11. 呉 政訓, 金子峰雄, コンポーネント間近接制約に基づいた混合誤り訂正機構と回路面積評価, 電子情報通信学会VLSI設計技術研究会 (IEICE Technical Report on VLSI Design Technology), VLD2016-129, pp.151-156 March 2017.
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2016 年 †

  1. Junghoon Oh, Mineo Kaneko, Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing, IEICE Trans. Fundations, Vol.E99-A, No.7, pp.1311-1322, July 2016.
  2. Renyuan Zhang, Mineo Kaneko, A 16-Valued Logic FPGA Architecture Employing Analog Memory Circuit, Proc. IEEE International Symposium on Circuits and Systems, pp. 718-721, (May 2016).
  3. Junghoon Oh, Mineo Kaneko, Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.595-600, July 2016 (Pittsburgh, Pennsylvania, USA).
  4. Junghoon Oh, Mineo Kaneko, Mixed Error Correction Scheme and Its Design Optimization for Soft-Error Tolerant Datapaths, Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp.362-365, October 2016 (Korea) .
  5. Mineo Kaneko, KKT-Condition Based Study on DVFS for Heterogeneous Task Set, Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp.717-720, October 2016 (Korea).
  6. Keisuke Inoue, Mineo Kaneko, MILP-based Scheduling for Clock Latency Minimization in High-level Synthesis, Proc. 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2016), pp.925-928, July 2016 (Okinawa).
  7. Makoto Soga, Mineo Kaneko, Optimization of Temperature Dependent Intentional Skew for Temperature Aware Timing Design, Proceedings of 20th Workshop on Synthesis and System Integration of Mixed Information Technologies, pp.119-124, October, 2016 (Kyoto).
  8. Renyuan Zhang, Mineo Kaneko,A Feasibility Study of Master-Slave Flipflop Design for Hexadecimal Logic, IEEE Industrial Electronics and Applications Conference, November, 2016.
  9. Mineo Kaneko, A Study on Multi-Level DVFS for Heterogeneous Task Set, Proc. of Design Automation Symposium, IPSJ, pp.146-150, September 2016.
  10. 勝又一穂, 金子峰雄, 製造後スキュー調整による動作速度最大化のためのデータパス資源割り当て, 電子情報通信学会VLSI設計技術研究会, VLD2015-141, pp.173-178, February 2016.
  11. Keisuke Inoue, Mineo Kaneko, A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis,, 電子情報通信学会VLSI設計技術研究会, VLD2015-117, pp. 37-42, February 2016.
  12. 呉政訓, 金子峰雄, コンポーネント間近接制約を考慮した整数線形計画法による耐ソフトエラーデータパス合成, 電子情報通信学会VLSI設計技術研究会, VLD2015-116, pp.31-36, February 2016.
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2015 年 †

  1. 呉政訓, 金子峰雄, コンポーネント間近接制約を考慮した耐ソフトエラーデータパス合成, 電子情報通信学会VLSI設計技術研究会, VLD2015-62, pp.159-164, December 2015.
  2. Mineo Kaneko, A Study on DVFS for Heterogeneous Task Set, 電子情報通信学会VLSI設計技術研究会, VLD2015-47, pp. 63-68, December 2015.
  3. Renyuan Zhang, Mineo Kaneko, Robust and Low-Power Digitally-Programmable-Delay-Element Designs Employing Neuron-MOS Mechanism, ACM Transactions on Design Automation of Electronic Systems, Vol. 20, No. 4, Article 64 (19 pages), September 2015.
  4. Keisuke Inoue, Mineo Kaneko, Bitwidth-Aware Register Allocation and Binding for Clock Period Minimization, Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 499-502, August 2015.
  5. Renyuan Zhang, Mineo Kaneko, A Feasibility Study of Quaternary FPGA Designs by Implementing Neuron-MOS Mechanism, Proc. IEEE International Symposium on Circuits and Systems, pp. 942-945, May 2015.
  6. Junghoon Oh, Mineo Kaneko, Automated Selection of Check Variables for Area-Efficient Soft-Error Tolerant Datapath Synthesis, Proc. IEEE International Symposium on Circuits and Systems, pp.49-52, May 2015.
  7. Mineo Kaneko, A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling, Proceedings of ACM Great Lakes Symposium on VLSI, pp.367-372, May 2015.
  8. Junghoon Oh, Mineo Kaneko, Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing in Triple Algorithm Redundancy, Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), pp.272-277, March 2015.
  9. Renyuan Zhang, Mineo Kaneko, A Quaternary Master-Slave Flip-Flop with Multiple Functions for Multi-Valued Logics, Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), pp.193-198, March 2015.
  10. 呉政訓, 金子峰雄, 整数線形計画法による高面積効率耐ソフトエラーデータパス回路合成, 電子情報通信学会VLSI設計技術研究会, VLD2014-164, pp.67-72, March 2015.
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2014 年 †

  1. Renyuan Zhang, Mineo Kaneko, A Temperature and Process Variation Insensitive PDE Circuit Employing Neuron-MOS, IEEE/ACM Workshop on Variability Modeling and Characterization (VMC) 2014, November 2014.
  2. Mineo Kaneko, Timing-Test Scheduling for PDE Tuning Considering Multiple-Path Testability, 電子情報通信学会VLSI設計技術研究会, VLD2014-94, DC2014-48, pp.149-154, November 2014.
  3. Mineo Kaneko, Yutaka Tsuboishi, Constrained Binding and Scheduling of Triplicated Algorithm for Fault Tolerant Datapath Synthesis, Proceedings of IEEE International Symposium on Circuits and Systems, pp.1448-1451, June 2014.
  4. H. Nishiyama, M. Inagi, S. Wakabayashi, S. Nagayama, K. Inoue, M. Kaneko, An ILP-based Optimal Circuit Mapping Method for PLDs, Proceedings of IEEE Reconfigurable Architectures Workshop (RAW 2014), pp.-, May 2014.
  5. Mineo Kaneko, Scheduling of PDE Setting and Timing Tests for Post-Silicon Skew Tuning with Timing Margin --Extended Abstract--, Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp.91-92, May 2014.
  6. Renyuan Zhang, Mineo Kaneko, A Feasible Study on Robust Programmable Delay Element Design Based on Neuron-MOS Mechanism, Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp.21-26, May 2014.
  7. 呉政訓, 金子峰雄, 積極的資源共有による高面積効率耐ソフトエラーデータパス回路の設計, 電子情報通信学会VLSI設計技術研究会, VLD2013-156, pp.119-124, March 2014.
  8. 久保辰徳, 金子峰雄, 極低電圧集積回路のための基板バイアス・タイミングスキュー同時調整, 電子情報通信学会VLSI設計技術研究会, VLD2013-163, pp.159-163, March 2014.
  9. 加藤孝太郎, 金子峰雄, 同期・非同期混合回路方式とその設計手法, 電子情報通信学会VLSI設計技術研究会, VLD2013-164, pp.165-170, March 2014.
  10. 立岡真人, 青木利晃, 金子峰雄, 再利用のためのRTLからの関数コード生成手法, 電子情報通信学会VLSI設計技術研究会, VLD2013-165, pp.171-176, March 2014.
  11. Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim, System Design and Analysis for Maximum Consuming Power Control in Smart House, Journal of Automation and Control Engineering, Engineering and Technology Publishing, Vol. 2, No. 1, pp.43-48, March 2014 issue (October 2013 On-line publication).
  12. Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim, Priority Based Maximum Consuming Power Control in Smart Homes, 5th Innovative Smart Grid Technologies Conference, February 2014.
  13. Renyuan Zhang, Mineo Kaneko, A Feasible Study of Robust and Low-Power Programmable Delay Elements Based on Neuron-MOS Mechanism, Papers of Technical Meeting on Electronic Curcuits, IEE Japan, No. ECT-14-15, pp.75-80, January 2014.
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2013 年 †

  1. Keisuke Inoue and Mineo Kaneko, Dual-edge-triggered Flip-flop-based High-level Synthesis with Programmable Duty Cycle, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol.E96-A, No.12, pp.2689-2697, December 2013.
  2. Mineo Kaneko, Scheduling of PDE Setting and Timing Test for Post Silicon Skew Tuning, IEICE Technical Report, VLD2013-98, DC2013-64, pp.269-274, November 2013.
  3. Renyuan Zhang, Mineo Kaneko, Tadashi Shibata, A Fully-Parallel Self-Learning Analog Support Vector Machine Employing Compact Gaussian-Generation Circuit, Proceedings of International Conference on Solid-State Devices and Materials, pp.174-175, September 2013.
  4. Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim, System Design and Analysis for Maximum Consuming Power Control in Smart House, International Conference on Power and Energy Engineering, September 2013.
  5. Keisuke Inoue and Mineo Kaneko, Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-flops and Latches, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol.E96-A, No.8, pp.1712-1722, August 2013.
  6. 立岡真人, 金子峰雄, 既存RTL資産の高位からの再合成アプローチ, 電子情報通信学会 VLSI設計技術研究会, VLD2012-145, pp.55-60, March 2013.
  7. Mineo Kaneko, Test Planning for Post-Silicon Skew Tuning Based on Graph Partitioning, IEICE Technical Report, VLD2012-159, pp.129-133, March 2013.
↑

2012 年 †

  1. Keisuke Inoue and Mineo Kaneko, A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-skew Tolerant Datapaths, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol.E95-A, No.12, pp.2330-2337, December 2012.
  2. Mineo Kaneko, Dynamic Timing-Test Scheduling for Post-Silicon Skew Tuning, IEICE Technical Report, VLD2012-85, DC2012-51, pp.153-158, November 2012.
  3. Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim, Energy Stability-aware Scheme for Intelligent Home Energy Management Systems, IPSJ SIG Technical Report, Vol. 2012-MBL-64, No.21, pp.1-6, November 2012.
  4. Mineo Kaneko, Timing-Test Scheduling for Constraint-Graph Based Post-Silicon Skew Tuning, Proceedings of IEEE International Conference on Computer Design (ICCD), pp.460-465, October 2012.
  5. Keisuke Inoue and Mineo Kaneko, Statistical Timing-Yield Driven Scheduling and FU Binding in Latch-Based Datapath Synthesis, Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp.631-634, August 2012.
  6. Mineo Kaneko and Li Jian, Post-Silicon Skew Tuning Algorithm Utilizing Setup and Hold Timing Tests, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp.125-128, May 2012.
  7. Keisuke Inoue and Mineo Kaneko, Reliable and Low-Power Clock Distribution Using Pre- and Post-Silicon Delay Adaptation in High-Level Synthesis, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp.1664-1667, May 2012.
  8. Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, and Hafiz Md. Hasan Babu, An Efficient Approach for Designing and Minimizing Reversible Programmable Logic Arrays, Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp.215-220, May 2012.
  9. Keisuke Inoue and Mineo Kaneko, Optimal Register-Type Selection during Resource Binding in Flip-Flop/Latch-Based High-Level Synthesis, Proceedings of IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.79-82, May 2012.
  10. Keisuke Inoue and Mineo Kaneko, Register Binding and Domain Assignment for Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis, Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp.778-783, March 2012.
  11. 春田 洋佑, 金子 峰雄, 製造後スキュー調整性を最大化するRTL資源割当手法, 電子情報通信学会 技術報告 (VLSI設計技術研究会), March 2012.
  12. Keisuke Inoue and Mineo Kaneko, Performance-Driven Register Write Inhibition in High-Level Synthesis under Strict Maximum-Permissible Clock Latency Range, Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp.239-244, January 2012.
↑

2011 年 †

  1. Tsuyoshi Iwagaki, Eiri Takeda, and Mineo Kaneko, Flexible Test Scheduling for an Asynchronous On-chip Interconnect through Special Data Transfer, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, vol. E94-A, no. 12, pp. 2563-2570, December 2011.
  2. Mineo Kaneko, A Basic Study on Timing-Test Scheduling for Post-Silicon Skew Tuning, IEICE Technical Report (VLD), November 2011.
  3. Keisuke Inoue and Mineo Kaneko, Early Planning for RT-Level Delay Insertion during Clock Skew-Aware Register Binding, Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp.154-159, October 2011.
  4. Keisuke Inoue and Mineo Kaneko, Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis, IEICE Technical Report (VLD), pp.61-66, September 2011.
  5. Keisuke Inoue and Mineo Kaneko, On the NP-Hardness of Minimum-Period Register Binding, The IEICE 2011 Engineering Sciences Society Conference, A-1-15, September 2011.
  6. 李 健, 金子 峰雄, タイミングテストを利用するLSI製造後スキュー調整アルゴリズム, 電子情報通信学会 2011年ソサイエティ大会, A-3-17, September 2011.
  7. Keisuke Inoue and Mineo Kaneko, Framework for Latch-Based High-Level Synthesis using Minimum-Delay Compensation, IPSJ Transactions on System LSI Design Methodology (TSLDM), vol. 4, pp. 232-244, August 2011.
  8. Keisuke Inoue and Mineo Kaneko, Operation Scheduling Considering Time Borrowing for High-Performance Latch-Based Circuits, Proceedings of IEEE International NEWCAS Conference (NEWCAS), pp.245-248, June 2011.
  9. Tsuyoshi Iwagaki and Kewal K. Saluja, Power-Constrained Test Generation for Hold-Time Faults Using Integer Linear Programming, Proceedings of IEEE International Workshop on the Impact of Low Power design on Test and Reliability (LPonTR), 2 pages, May 2011.
  10. Keisuke Inoue and Mineo Kaneko, Variable-Duty-Cycle Scheduling in Double-Edge-Triggered Flip-Flop-Based High-Level Synthesis, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp.550-553, May 2011.
  11. Mineo Kaneko and Keisuke Inoue, Ordered Coloring-Based Resource Binding for Datapaths with Improved Skew-Adjustability, Proceedings of IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.307-312, May 2011.
  12. Tsuyoshi Iwagaki and Kewal K. Saluja, Indirect Detection of Clock Skew Induced Hold-Time Violations on Functional Paths Using Scan Shift Operations, Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp.175-178, April 2011.
  13. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, vol.E94-A, no.4, pp.1067-1081, April 2011. 電子情報通信学会 基礎境界ソサイエティ論文賞受賞
  14. Mineo Kaneko, A Complete Framework of Simultaneous Functional Unit and Register Binding with Skew Scheduling, Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp.189-195, March 2011.
  15. Tsuyoshi Iwagaki and Kewal K. Saluja, On Indirect Detection of Functional Hold-Time Violations Using Scan Shift Operations,電子情報通信学会技術報告 (機能集積情報システム研究会), FIIS-11-298, pp.1-5, March 2011.
  16. 曽和修一, 金子峰雄, 準相補MOSを用いたデジタル回路の低消費電力化設計, 電子情報通信学会 技術報告 (VLSI設計技術研究会), VLD2010-122, pp.37-42, March 2011.
  17. 党羽, 金子峰雄, 速度性能とタイミングスキュー調整特性に優れたデータパスの合成手法, 電子情報通信学会 技術報告 (VLSI設計技術研究会), VLD2010-133, pp.99-104, March 2011.
↑

2010 年 †

  1. Keisuke Inoue and Mineo Kaneko, Optimal Register Assignment with Minimum-Delay Compensation for Latch-Based Design, Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 887-890, December 2010.
  2. Tsuyoshi Iwagaki, Eiri Takeda, and Mineo Kaneko, An Approach to Test Scheduling for Asynchronous On-Chip Interconnects Using Integer Programming, Digest of Papers 11th IEEE Workshop on RTL and High Level Testing (WRTLT '10), pp. 69-74, December 2010.
  3. 上杉伸, 金子峰雄, コードベース三次元直方体配置における隣接挿入操作とその効果, 電子情報通信学会技術報告 (VLSI設計技術研究会), VLD2010-77, DC2010-44, pp.149-154, December 2010
  4. Mineo Kaneko, ILP Approach to Extended Ordered Coloring for Skew Ajdustability-Aware Resource Binding, IEICE Technical Report, VLD2010-75, DC2010-42, pp.131-136, December 2010
  5. 金子峰雄, [招待講演] 部品配置の一アプローチ: Sequence Pair とその展開, 電子情報通信学会技術報告 (回路とシステム研究会), CAS2010-76, CST2010-49, p.63, November 2010.
  6. Keisuke Inoue and Mineo Kaneko, A Novel IR-Drop Tolerant Scheduling for Reliability-Aware Datapaths, Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 76-81, October 2010.
  7. Mineo Kaneko and Takayuki Shibata, Extended Sequence Pair: A Finite Solution Space for Two-Directional Repeated Placement, Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI), pp.190--195, October 2010.
  8. Mineo Kaneko, Ordered Coloring for Skew Adjustability-Aware Resource Binding, 電子情報通信学会技術報告 (VLSI設計技術研究会), VLS2010-42, pp.1-6, September 2010.
  9. Keisuke Inoue and Mineo Kaneko, Adjustable Safe Clocking-Based Register Assignment Considering the Setup and Hold Timing Constraints, Proceedings of IPSJ DA Symposium, pp. 81-86, September 2010.
  10. Keisuke Inoue and Mineo Kaneko, Minimizing Clocking Patterns of Adjustable safe Clocking for Timing Variation-Aware Datapaths, Proceedings of IEEE Mid-West Symposium on Circuits and Systems (MWSCAS), pp.113-116, August 2010.
  11. Keisuke Inoue and Mineo Kaneko, Clocking Pattern Minimization for Adjustable Safe Clocking-Based Register Assignment, Proceedings of IEICE Technical Report (CAS), vol. 110, no. 86, pp. 1-6, June 2010.
  12. Tsuyoshi Iwagaki, Eiri Takeda, and Mineo Kaneko, Test Scheduling Algorithms for Delay-Insensitive Chip Area Interconnects Based on Cone Partitioning, Proceedings of 3'rd International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR 2010), 2 pages, May 2010. (at Czech Republic)
  13. Keisuke Inoue and Mineo Kaneko, A Novel Resource Sharing Model and High-Level Synthesis for Delay Variability-Tolerant Datapaths, Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 111-114, May 2010.
  14. 井上恵介, 金子峰雄, 整数計画法による高位合成基本タスクの記述, 電子情報通信学会 回路とシステム軽井沢ワークショップ予稿集, pp.185--190, April 2010.
  15. 佐藤円, 金子峰雄, メッシュグラフ埋め込みにおける埋め込みパターンと関連操作 , 電子情報通信学会技術報告 (回路とシステム研究会), CAS2009-90, SIP2009-135, CS2009-85, pp.69-74, March 2010.
  16. 武田英理, 岩垣剛, 金子峰雄, コーン分割を用いた非同期インターコネクトの効率的なテストスケジューリング法, 電子情報通信学会 (機能情報集積システム研究会), FIIS-10-272, March 2010.
  17. 手原亮, 金子峰雄, タイミングスキュー調整可能データパスの合成条件, 電子情報通信学会技術報告 (VLSI設計技術研究会), VLD2009-122, pp.139-144, March 2010.
  18. Tsuyoshi Iwagaki and Mineo Kaneko, A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties, Proceedings of IEEE International Symposium on Electronic Design, Test and Applications (DELTA), pp.293-296, January 2010.
↑

2009 年 †

  1. 井上恵介, 金子峰雄, 高位合成の完全ILP記述に基づくマルチプレクサの最小化, 電子情報通信学会技術報告 (VLSI設計技術研究会), VLD2009-43, pp.13-18, December 2009.
  2. 井上恵介, 金子峰雄, 整数計画法によるグラフ埋め込みの定式化とLSI配線問題への応用, 電子情報通信学会技術報告 (回路とシステム研究会), CAS2009-56, pp.65-70, November 2009.
  3. 井上恵介,金子峰雄, 計算機実験によるデータパスの遅延変動耐性評価 平成21年度電気関係学会東海支部連合大会, September 2009.
  4. 井上恵介,金子峰雄, エッジリスト付き彩色問題の計算複雑度とアルゴリズムについて 電子情報通信学会 ソサイエティ大会 基礎・境界講演論文集, A-1-9, p.9, September 2009, 学術奨励賞受賞(文献14と合わせて).
  5. Tsuyoshi Iwagaki, Mineo Kaneko, A Heuristic Approach to Detecting Transition Faults at All Circuit Outputs, 電子情報通信学会 ソサイエティ大会 基礎・境界講演論文集, A-3-5, , p.54, September 2009.
  6. 手原亮, 金子峰雄, LSI製造ばらつきに対するデータパス制御タイミングのスキュー調整成功率, 電気関係学会北陸支部連合大会, B-4, September 2009.
  7. Keisuke Inoue and Mineo Kaneko, Complete ILP Formulation of High-Level Synthesis, IEICE Technical Report (VLD), VLD2009-32, pp.19-24, September 2009.
  8. Keisuke Inoue, Takanuki Obata, Yayumi Uehara, and Mineo Kaneko, Optimal stall insertion with timing skew adjustment for tunable LSIs, Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp.1187-1190, August 2009.
  9. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Resource Sharing and Scheduling Algorithms against Variation of Control Timings, IEICE Technical Report (CAS), CAS2009-5, VLD2009-10, SIP2009-22, pp.25-30, July 2009.
  10. Takayuki Obata and Mineo Kaneko, Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1521-1524, May 2009.
  11. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Safe Clocking for the Setup and Hold Timing Constraints in Datapath Synthesis, Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 27-32, May 2009.
  12. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Safe Clocking-Based Datapath Synthesis for the Setup and Hold Timing Constraints, IEICE Circuits and Systems KARUIZAWA Workshop, pp. 432-437, April 2009.
  13. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol.E92-A, No.4, pp. 1096-1105, April 2009.
  14. Keisuke Inoue and Mineo Kaneko, A Note on the NP-Completeness of the Ordered Coloring on Unit Interval Graphs, 電子情報通信学会 総合大会 No.A-1-16, 基礎・境界講演論文集, p. 16. Mar. 2009, 学術奨励賞受賞(文献4と合わせて).
  15. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Adjustable Safe Clocking and Relevant Register Assignment in Datapath Synthesis, IEICE Technical Report, VLD2008-130, pp.23-28, March 2009.
  16. 坪石優, 金子峰雄, 冗長化アルゴリズムからの耐故障データパス自動合成, 電子情報通信学会技術報告 (VLSI設計技術研究会), VLD2008-132, pp.35-40, March 2009.
  17. Tsuyoshi Iwagaki and Mineo Kaneko, On the Derivation of a Minimum Test Set in High Quality Transition Testing, Proceedings of IEEE Latin-American Test Workshop, pp. 1-6, March 2009.
  18. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, A Conjecture on the Number of Extra Registers in Safe Clocking-Based Register Assignment, Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI), pp. 131-136, March 2009.
  19. 上原八弓, 金子峰雄, 制御のタイミングスキューおよびストールに基づくLSIチューニング, 電子情報通信学会技術報告 (VLSI設計技術研究会), VLD-2008-106, pp. 87-92, January 2009.
  20. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, A Note on the Number of Extra Registers in Safe Clocking-Based Register Assignment, IEICE Technical Report (CAS), CAS-2008-90, pp. 147-152, January 2009.
↑

2008 年 †

  1. Takayuki Obata, Mineo Kaneko, Simultaneous Optimization of Skew and Control Step Assignment in RT-Datapath Synthesis, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol. E91-A, No. 12, pp.3585-3595, December 2008.
  2. 小畑 貴之, 金子 峰雄, スキュー最適化を前提とするデータパス合成におけるスケジュール可能解空間の拡大, 電子情報通信学会技術報告 (VLSI設計技術研究会), VLD2008-86, pp. 157-162, November 2008.
  3. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Delay Variability-Aware Datapath Synthesis Based on Safe Clocking for Setup and Hold Timing Constraints, IEICE Technical Report (VLD), VLD2008-85, pp. 151-156, November 2008.
  4. Tsuyoshi Iwagaki and Mineo Kaneko, An Integer Programming Formulation for Generating High Quality Transition Tests, IEICE Technical Report (DC), DC2008-29, pp. 7-12, November 2008.
  5. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Safe Clocking Register Assignment in Datapath Synthesis, Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 120-127, October 2008.
  6. Takayuki Obata, Mineo Kaneko, スキュー最適化を前提とした実行可能な資源割り当て及び演算順序, IEICE Technical Report (VLD), VLD2008-50, pp.19-24, September 2008.
  7. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Delay Variation-Aware Datapath Synthesis Based on Register Clustering, IEICE Technical Report (VLD), VLD2008-51, pp. 25-30, September 2008.
  8. 井上 恵介, 金子 峰雄, 岩垣 剛, データパス合成における順序制約付レジスタ割り当て問題の解法, DAシンポジウム, pp. 115-120, August 2008.
  9. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Minimizing Minimum Delay Compensations for Timing Variation-Aware Datapaths Synthesis, Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. 97-100, August 2008.
  10. 金子 峰雄, [招待講演] 先端LSIのための高位合成問題, 電子情報通信学会技術報告 (コンピュテーション研究会), June 2008.
  11. 井上 恵介, 金子 峰雄, 岩垣 剛, 高位合成における順序制約付レジスタ割り当て, 電子情報通信学会技術報告 (VLSI設計技術研究会), VLD2008-33, pp. 7-12, June 2008.
  12. Takayuki Obata, and Mineo Kaneko, Concurrent Skew and Control Step Assignments in RT-Level Datapath Synthesis, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2018-2021, May 2008.
  13. 井上 恵介, 金子 峰雄, 岩垣 剛, データパス合成における最小遅延補正演算器数の最小化手法, 電子情報通信学会 回路とシステム軽井沢ワークショップ, pp. 623-628, April 2008.
  14. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Novel Register Sharing in Datapath for Structural Robustness against Delay Variation, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, vol. E91-A, no. 4, pp. 1044-1053, April 2008.
  15. 井上 恵介, 金子 峰雄, 岩垣 剛, データパス合成における最小遅延補正演算器数の最小化手法, 電子情報通信学会技術報告 (VLSI設計技術研究会), VLD2007-140, pp. 19-24, March 2008.
  16. 竹ヶ原 正晃, 岩垣 剛, 金子 峰雄, C素子展開に基づく2線2相式回路のテスト生成法, 電子情報通信学会技術報告 (ディペンダブルコンピューティング研究会), (口頭発表のみ), February 2008.
↑

2007 年 †

  1. 柴田 貴之, 金子 峰雄, 二次元トーラス空間内の矩形配置に対するコード表現手法, 電子情報通信学会技術報告 (回路とシステム研究会), CAS2007-80, pp.37-42, November 2007.
  2. Takayuki Obata and Mineo Kaneko, A Schedule Improvement with Skew Control in Datapath Synthesis, 電子情報通信学会技術報告 (VLSI設計技術研究会), VLD2007-94, pp.31-36, November 2007.
  3. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Complexities and Algorithms of Minimum-Delay Compensation Problems in Datapath Synthesis, 電子情報通信学会技術報告 (VLSI設計技術研究会), VLD2007-93, pp. 25-30, November 2007.
  4. Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko and Hideo Fujiwara, Efficient Path Delay Test Generation Based on Stuck-at Test Generation Using Checker Circuitry, Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 418-423, November 2007.
  5. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Structural Robustness of Datapaths against Delay-Variations, Proceedings of Workshop on Synthesis and System Integration of Mixed Information technology (SASIMI), pp. 272-279, October 2007.
  6. Yuuki Yano and Mineo Kaneko, Solution Space Reduction of Sequence Pairs using Model Placement, Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1130-1133, August 2007.
  7. Takayuki Obata and Mineo Kaneko, Re-Scheduling with Skew Optimization in RT-Datapath Synthesis, 電子情報通信学会技術報告 (回路とシステム研究会), CAS2007-24, pp. 31-36, June 2007.
  8. Khin Thida Latt, Mineo Kaneko, and Yoichi Shinoda, Parallel Computation of Data Summation for Multiple Problem Spaces on Partitioned Optical Passive Stars Network, International Journal of Electronics, Circuits and Systems, Vol. 1, No. 2, pp. 110-115, June 2007.
  9. Khin Thida Latt, Mineo Kaneko, and Yoichi Shinoda, Parallel Computation of Data Summation for Multiple Problem Spaces on Partitioned Optical Passive Stars Network, International Conference on Parallel and Distributed Computing Systems, May 2007.
  10. 井上 恵介, 金子 峰雄, 岩垣 剛, データパスにおける遅延変動耐性に関する基礎的考察, 回路とシステム軽井沢ワークショップ予稿集, pp. 649-654, April 2007.
  11. Koji Ohashi and Mineo Kaneko, Extended Register-Sharing in the Synthesis of Dual-Rail Two-Phase Asynchronous Datapath, Proceedings of IEEE/ACM Great Lakes Symposium on VLSI, pp. 481-484, March 2007.
  12. 矢野 勇生，金子 峰雄， 配線長を考慮した半順序制約付きシーケンスペアによるモジュール配置の評価と考察, 電子情報通信学会技術報告 (回路とシステム研究会), CAS2006-88, pp.63-68, March 2007.
  13. Koji Ohashi and Mineo Kaneko, Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol. E90-A, No.3, pp.659-669, March 2007.
  14. Koji Ohashi and Mineo Kaneko, Loop Pipeline Scheduling for Assignment Constrained Iteration Period Minimization, WSEAS Transactions on Circuits and Systems, Vol. 6, No. 3, pp.389-396, March 2007.
  15. Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, and Hideo Fujiwara, A Test Generation Framework Using Checker Circuits and Its Application to Path Delay Test Generation, IEICE Technical Report (CAS), CAS2006-76, Vol. 106, No. 512, pp.37-42, January 2007.
  16. Takayuki Obata and Mineo Kaneko, Computational Complexity of Simultaneous Optimization of Skew, Schedule and Clock in High-Level Synthesis, IEICE Technical Report (CAS), CAS2006-75), Vol. 106, No. 512, pp. 31-36, January 2007.
↑

2006 年 †

  1. Mineo Kaneko, Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules, Proceedings of IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), pp. 335-338, December 2006.
  2. Takayuki Obata and Mineo Kaneko, Computational Complexity of Simultaneous Optimization of Control Schedule and Skew in Datapath Synthesis, IEICE Techinical Report (VLD2006-65), November 2006.
  3. 井上 恵介, 金子 峰雄, 岩垣 剛, 遅延ばらつきを考慮したデータパス合成に関する基礎的考察, 電子情報通信学会技術報告 (VLSI設計技術研究会) (VLD2006-64), pp. 77-82, November 2006.
  4. 矢野 勇生, 金子 峰雄, 二次配線長最小化を利用したシーケンスペアの解空間縮小, 電子情報通信学会技術報告 (回路とシステム研究会) (CAS2006-59), pp. 25-30, November 2006.
  5. 小畑 貴之, 金子 峰雄, データパス合成における制御信号のスキュー付コントロールステップ割当問題の計算量について, 電子情報通信学会ソサイエティ大会, S-3, September 2006. Mineo Kaneko, Statistical Property and Subclass Structure of Sequence Triple Code Space for Repeated Placements, Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2006.
  6. Koji Ohashi and Mineo Kaneko, Analysis and Optimization of Statistical Performance for Asynchronous Datapaths, WSEAS Transactions on Circuits and Systems, Vol. 5, No. 7, pp. 895-902, July 2006.
  7. Koji Ohashi and Mineo Kaneko, Statistical Makespan Analysis in Asynchronous Datapath Synthesis, Proceedings of 10th WSEAS International Conference on Circuits, pp. 318-323, July 2006.
  8. Koji Ohashi and Mineo Kaneko, Dual-Rail Two-Phase Asynchronous Datapath Synthesis Based on Aggressive Register Sharing Model, Proceedings of 19th Workshop on Circuits and Systems in Karuizawa, pp. 589-594, April 2006.
  9. Takayuki Obata and Mineo Kaneko, Simultaneous Control-Step and Skew Assignment for Control Signals in RT-Level Datapath Synthesis, Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 314-321, April 2006.
  10. Mineo Kaneko, Solution Space Reduction of Sequence Pairs using Model Placement, IEICE Technical Report (CAD2006-5), pp. 25-28, June 2006.
  11. 小畑 貴之, 金子 峰雄, 平石 邦彦, 温度並列 SA のシーケンスペアによるパッキング問題への適用, 電子情報通信学会総合大会, March 2006.
  12. Koji Ohashi and Mineo Kaneko, Resource Sharing in Dual-Rail Two-Phase Asynchronous Datapath Synthesis, Technical Report of IEICE (CAS2005-93), Vol. 105, No. 504, pp. 37-42, January 2006.
  13. Takayuki Obata and Mineo Kaneko, Simultaneous Control-Step and Skew Assignment for Control Signals in RT-Level Datapath Synthesis, Technical Report of IEICE (CAS2005-92), Vol. 105, No. 504, pp. 31-36, Jan. 2006.
↑

2005 年 †

  1. Mineo Kaneko, Minimal Set of Essential Lifetime Overlaps for Exploring 3D Schedule, Technical Report of IEICE (VLD2005-64), Vol. 105, No. 442, pp. 19-24, December 2005.
  2. Koji Ohashi and Mineo Kaneko, Statistical analysis driven synthesis of asynchronous systems, Proc. IEEE International Conference on Computer Design (ICCD), pp. 200-205, October 2005.
  3. Mineo Kaneko, Sequence Triple: A Finite Solution Space for Repeated Placement, Proc. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1446-1449, August 2005.
  4. Takayuki Obata and Mineo Kaneko, Control Signal Skew Scheduling in RT Level Datapath Synthesis, Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1087-1090, August 2005.
  5. Koji Ohashi and Mineo Kaneko, Statistical Schedule Length Analysis in Asynchronous Datapath Synthesis, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 700-703, May 2005.
  6. Koji Ohashi and Mineo Kaneko, Simultaneous Scheduling and Binding for Asynchronous System with Statistical Makespan Analysis, Proceedings of 18th Workshop on Circuits and Systems in Karuizawa, pp. 587-592, April 2005.
  7. Takayuki Obata and Mineo Kaneko, Control Signal Skew Scheduling for RT Level Datapaths, Proceedings of Workshop on Circuits and Systems in Karuizawa, pp. 521-526, April 2005.
  8. Takayuki Obata and Mineo Kaneko, Control signal skew scheduling for RT level datapaths, Technical Report of IEICE (CPSY2004-107), pp. 13-17, March 2005.
  9. Koji Ohashi and Mineo Kaneko, Statistical Schedule Length Analysis in Asynchronous Datapath Synthesis, Technical Report of IEICE (CAS2004-72), Vol. 104, No. 557, pp. 1-5, January 2005.
  10. Mineo Kaneko and Tomoyuki Ogawa, A Finite Solution Space for Recurrent Placements, Technical Report of IEICE (CAS2004-73), Vol. 104, No. 557, pp. 7-12, January 2005.
  11. Takayuki Obata and Mineo Kaneko, Simultaneous Scheduling and Skew Assignment for Multiplexer Control in Placed Datapaths, Technical Report of IEICE (CAS2004-74), Vol.104, No.557, pp. 13-18, January 2005.
↑

2004 年 †

  1. Mineo Kaneko and Koji Ohashi, Assignment Constrained Scheduling under Max/Min Logic/Interconnect Delays for Placed Datapath, Proceedings of IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), Vol. 1, pp. 545-548, December 2004.
  2. Koji Ohashi and Mineo Kaneko, Asynchronous Datapath Synthesis Enhancing Graceful Degradation for Delay Faults, Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 303-309, October 2004.
  3. Koji Ohashi and Mineo Kaneko, Asynchronous Datapath Synthesis Based on Binding Space Exploration, Proceedings of Workshop on Circuits and Systems in Karuizawa, pp. 49-554, April 2004.
↑

2003 年 †

  1. Mineo Kaneko and Kazuaki Oshio, Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism, Proc. International Symposium on Circuits and Systems, Vol. V, pp. 645-648, May 2003.
  2. 小畑 貴之, 金子 峰雄, 田湯 智, 資源割り当て駆動スケジューリングにおけるレジスタ間転送の自動挿入, 電子情報通信学会技術報告 (VLD2003-2), Vol. 103, No. 40, pp. 7-12, May 2003.
  3. 厚見 吉彦, 大橋 功治, 金子 峰雄, 計算アルゴリズムの局所的類似性とそのデータパス合成への応用, 電子情報通信学会技術報告 (VLD2003-3), vol. 103, no. 40, pp. 13-18, May 2003.
  4. Koji Ohashi and Mineo Kaneko, Binding constrained scheduling for iterative algorithm with conditional branches, Proc. Workshop on Synthesis and System Integration of Mixed Information technology, pp. 144-151, April 2003.
  5. Mineo Kaneko and Koji Ohashi, Post-floorplan control schedule under max/min logic/interconnect delays, Proc. 16th Workshop on Circuits and Systems in Karuizawa, pp. 195-200, April 2003.
  6. 小原 正寛, 高島 康裕, 金子 峰雄, 回路階層構造の動的再構成を伴う力学的手法に基づくフロアプラン合成, 電子情報通信学会技術報告 (VLD2002-148), vol. 102, no. 683. pp. 13-18, March 2003.
↑

2002 年 †

  1. Satoshi Tayu and Mineo Kaneko, Characterization and Computation of Stiner Tree Routing Based on Elmore's Delay Model, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol. E85-A, No. 12, pp. 2764-2774, December 2002.
  2. Satoshi Tayu and Mineo Kaneko, The Width Constrained Placement by The Simulated Annealing with The Sequence-Pair Encoding, Technical Report of IEICE (VLD2002-100), Vol. 102, No. 476, pp. 109-114, November 2002.
  3. Satoshi Tayu and Mineo Kaneko, Characterization and Computation of Stiner Wiring Based on Elmore's Delay Model, Proceedings of Asia Pacific Conference on Circuits and Systems (APCCAS), Vol. 2, pp. 335-340, October 2002.
  4. Yasuhiro Takashima, Akira Kaneko, Shinji Sato and Mineo Kaneko, Two-Dimensional Placement Method Based on Divide-and-Replacement, Proceedings of Asia Pacific Conference on Circuits and Systems (APCCAS), Vol. 2, pp. 341-346, October 2002.
  5. Koji Ohashi and Mineo Kaneko, Heuristic Assignment-Driven Scheduling for Datapath Synthesis, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Vol. IV, pp. 703-706, May 2002.
  6. Mineo Kaneko, Jun'ichi Yokoyama and Satoshi Tayu, 3D Scheduling Based on Code Space Exploration for Dynamically Reconfigurable Systems, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Vol. V, pp. 465-468, May 2002.
  7. Satoshi Tayu, Takayuki Obata and Mineo Kaneko, Efficient Search on Solution Space based on Sequence-Pair for Simulated Annealing Approach, Technical Report of IEICE (VLD2002-5), Vol. 102, No. 72, pp. 25-30, May 2002.
  8. Kasuaki Oshio and Mineo Kaneko, Fault Tolerant Datapath Based on Algorithmic Redundancy and Voting, Techinical report of IEICE (VLD2002-11), Vol. 102, No. 73, pp. 19-24, May 2002.
  9. Toshiyuki Yorozuya, Koji Ohashi and Mineo Kaneko, Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol. E85-A, No. 4, pp. 819-826, April 2002.
  10. 高島 康裕, 金子 哲, 佐藤 眞司, 金子 峰雄, 分割および再配置に基づく2次元配置最適化手法, 第 15 回回路とシステム軽井沢ワークショップ, pp. 113-118, April 2002.
  11. Koji Ohashi and Mineo Kaneko, Minimization of Iteration Period in Assignment-Constrained Schedule for Datapath Synthesis, Proceedings of 15th Workshop on Circuits and Systems in Karuizawa, pp. 441-446, April 2002.
  12. 金子 哲, 高島 康裕, 佐藤 眞司, 金子 峰雄, 繰り返し分割再配置による 2 次元配置最適化手法, 電子情報通信学会技術研究報告 (VLD2001-146), Vol. 101, No. 694, pp. 1-8, March 2002.
↑

2001 年 †

  1. Mineo Kaneko, Reliable Data Routing for Spatial-Temporal TMR Multiprocessor Systems, IEICE Transactions on Information and Systems, Vol. E84-D, No. 12, pp. 1790-1800, December 2001.
  2. Koji Ohashi and Mineo Kaneko, Assignment-Driven Heuristic Scheduling Based on Sensitivity to Iteration Period for Datapath Synthesis, Technical Report of IEICE, VLD2001-105, pp. 97-102, November 2001.
  3. Mineo Kaneko and Yasuaki Maekawa, Extended Dimensional Threshold Filtering - A Bridge between FIR Filter and Median Type Filter, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2001.
  4. 平間 孝廉, 高島 康裕, 佐藤 真司, 金子 峰雄, Simulated Quenching 法に基づく 2 次元配置最適化手法, 電子情報通信学会, March 2001.
  5. 横山 順一, 金子 峰雄, 田湯 智, 3 次元パッキングに基づく動的再構成スケジューリング, 電子情報通信学会技術研究報告 (CAS2000-133), vol. 100, no. 717-722, pp. 43-50, March 2001.
  6. 萬屋 俊之, 大橋 功治, 金子 峰雄, 資源割り当て駆動パイプラインスケジューリングとその高位合成への応用, 電子情報通信学会技術研究報告 (VLD2000-141), vol. 100, no. 645-648, pp. 43-48 March 2001.
  7. Toshiyuki Yorozuya, Koji Ohashi and Mineo Kaneko, Assignment-Driven Loop Pipelining and Its Application to High Level Synthesis, Proceedings of Workshop on Synthesis and System Integration of Mixed Technology (SASIMI), January 2001.
↑

2000 年 †

  1. Mineo Kaneko, Yuuichiro Shimizu and Satoshi Tayu, Assignment-Space Exploration Approach to Testable Data-Path Synthesis for Minimizing Partial Scan Registers, Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 540-543, December 2000.
  2. Satoshi Tayu, Motoyasu Katsura and Mineo Kaneko, An Approximation Algorithm for Multiprocessor Scheduling of Trees with Communication Delays, Proceedings of International Symposium on Parallel Architectures, Algorithms, and Networks, pp. 114-120, December 2000.
  3. Koji Ohashi, Mineo Kaneko and Satoshi Tayu, Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis, Proceedings of IEEE International Conference on Computer Design: VLSI in Computers & Processors, pp. 370-375, September 2000
  4. Choon-Sik Park and Mineo Kaneko, An Efficient Scheme Based on Extended PDC Graph Model in Synthesizing Fault Tolerant FIR Filter, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 5, pp. 253-256, May 2000.
  5. Mineo Kaneko, Yoshikata Nishio and Satoshi Tayu, Exact and Heuristic Methods of Assignment Driven Scheduling for Data-Path Synthesis Applications, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 2, pp. 57-60, May 2000.
  6. Koji Ohashi, Mineo Kaneko and Satoshi Tayu, Assignment-Driven Approach to Data-Path Synthesis Incorporated with Floorplanning, Technical Report of IEICE, (VLD99-117), Vol. 99, No. 658-661, pp. 1-8, April 2000.
  7. 田湯 智, 桂 元保, 金子峰雄, 遅延を考慮した木構造タスクのスケジューリング, 電子情報通信学会, April 2000.
  8. 大橋 功治，金子 峰雄，田湯 智, 逐次的モジュール配置改善を伴うデータパス合成, 電子情報通信学会技術研究報告 (VLD99-117), Vol. 99, No. 659, pp. 1-8, March 2000.
  9. 金 泓徳，金子 峰雄，田湯 智, 大域的配線を考慮したフロアプランのためのグラフ平面化, 電子情報通信学会技術研究報告 (VLD99-121), Vol. 99, No.658-661, pp. 33-40, March 2000.
  10. Mineo Kaneko and Yasuaki Maekawa, Extended Dimensional Threshold Filtering: A Class on Nonlinear Filtering, Technical Report of IEICE (CAS99-111), Vol. 99, No. 552, pp. 1-8, Jan. 2000.
  11. 桂 元保，田湯 智，金子 峰雄, 先行制約付きタスクの通信時間を考慮した効率的スケジューリング, 電子情報通信学会技術研究報告 (CAS99-118), Vol. 99, No. 552, pp. 55-62, Jan. 2000.
↑

1999 年 †

  1. Choon-Sik Park and Mineo Kaneko, Checking Scheme for ABFT Systems Based on Modified PD Graph under an Error Generation/Propagation Model, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol. E82-A, No. 6, pp. 1002-1008, June 1999.
  2. Mineo Kaneko, Analysis and Suppression of Unnecessary Transitions in Weakly Complementary MOS Logic Networks for Low Power, Proceedings of IEEE Internatinal Symposium on Circuits and Systems (ISCAS), pp. 262-265, May 1999.
  3. 門地 忠夫, 田湯 智, 金子 峰雄, エルモア遅延モデルに基づく最大信号伝播遅延最小化スタイナー配線, 電子情報通信学会技術研究報告 (VLD98-135), Vol. 98, No. 624, pp. 27-34, March 1999.
  4. 志水 雄一郎, 金子 峰雄, スキャンレジスタ数の最小化を目的とするデータパス合成, 電子情報通信学会技術研究報告 (VLD98-146), Vol. 98, No. 625, pp. 41-47, March 1999.
  5. Yoshitaka Nishio, Mineo Kaneko and Satoshi Tayu, Assignment Based Approach to High Level Synthesis for Net Relevant Design Criteria, Technical Report of IEICE (VLD98-147), Vol. 98, No. 625, pp. 49-56, Mar. 1999.
↑

1998 年 †

  1. Mineo Kaneko, Reconfiguration of Folded Torus PE Networks for Fault Tolerant WSI Implementations, Proceedings of IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), pp. 791-794, November 1998.
  2. Choon-Sik Park and Mineo Kaneko, Checking Scheme for ABFT Systems Based on Modified PD Graph under An Error Generation/Propagation Model, Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1703-1706, July 1998.
  3. Fernando G. V. Resende, Paulo S. R. Diniz, Keiichi Tokuda, Mineo Kaneko, and Akinori Nishihara, New Adaptive Algorithms Based on Multi-Band Decomposition of The Error Signal, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 45, No. 5, pp. 592-599, May 1998.
  4. Mineo Kaneko, Scheduling and Reliability Aspects of Data Routing in Triplicated TMR Systolic/Multi-Processor Systems, Proceedings of International Conference on Massively Parallel Computer Systems, April 1998.
  5. Choon-Sik Park and Mineo Kaneko, An Efficient Technique for Design of ABFT Systems Based on Modified PD Graph, Proceedings of International Conference on Massively Parallel Computer Systems, April 1998.
  6. Mineo Kaneko, Scheduling and Reliability Aspects of Data Routing for Fault Tolerant Systolic Arrays, Technical Report of IEICE (VLD97-136), Vol. 97, No. 577, pp. 103-110, March 1998.
  7. Hiroshi Murata, Kunihiko Fujiyoshi, and Mineo Kaneko, VLSI/PCB Placement with Obstacles Based on Sequence Pair, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 1, pp. 60-68, January 1998.
↑

1997 年 †

  1. Fernando G. V. Resende, Paulo S. R. Diniz, Keiichi Tokuda, Mineo Kaneko, and Akinori Nishihara, LMS−Based Algorithms with Multi-Band Decomposition of The Estimation Error Applied to System Identification, 'The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol. E80-A, No. 8, pp. 1376-1383, August 1997.
  2. Fernando G. V. Resende, Paulo S. R. Diniz, Keiichi Tokuda, Mineo Kaneko, and Akinori Nishihara, Multi-Band Decomposition of The Linear Prediction Error Applied to The Least-Mean-Square Method with Fixed and Variable Step-Sizes, Proceedings of International Symposium on Circuits and Systems (ISCAS), Vol. 4, pp. 2176-2179, June 1997.
  3. Mineo Kaneko and Choon-Sik Park, Link Sharing for Reliable TMR Systolic Arrays, Technical Report of IEICE (CAS97-34), Vol. 97, No. 137, pp. 127-134, June 1997.
  4. Fernando G. V. Resende, Paulo S. R. Diniz, Mineo Kaneko, and Akinori Nishihara, Adaptive AR Spectral Estimation Based on Multi-Band Decomposition of The Linear Prediction Error with Variable Forgetting Factors, Proceedings of International Conference on Acoustics, Speech, and Signal Processing, pp. 2185-2188, April 1997.
  5. Hiroshi Murata, Kunihiro Fujiyoshi, and Mineo Kaneko, VLSI/PCB Placement with Obstacles Based on Sequence-Pair, Proceedings of International Symposium on Physical Design (ISPD), pp. 26-31, April 1997.
  6. 津曲 康史, 金子 峰雄, 計算処理オンライン誤り訂正の一最適設計, 電子情報通信学会技術研究報告 (VLD96-92), Vol. 96, No. 555, pp. 41-48, March 1997.
  7. 藤吉 邦洋, 三輪 剛史, 村田 洋, 金子 峰雄, ソフトモジュ-ルを含む配置問題の一解法, 電子情報通信学会技術研究報告 (VLD96-104), Vol. 96, No. 555, pp. 63-70, March 1997.
  8. Fernando G. V. Resende, Keiichi Tokuda, Mineo Kaneko, and Akinori Nishihara, Multi-Band Decomosition of The Linear Prediction Error Applied to Adaptive AR Spectral Estimation, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol. E80-A, No. 2, pp. 365-376, February 1997.
  9. Mineo Kaneko and Jialin Tian, Concurrent Cell Generation and Mapping for CMOS Logic Circuits, Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 247-252, January 1997.
↑

1996 年 †

  1. Mineo Kaneko and Hiroyuki Miyauchi, A Systematic Design of Fault Tolerant Systolic Arrays Based on Triple Modular Redundancy in Time-Processor Space, The IEICE Transactions on Information and Systems, Vol. E79-D, No. 12, pp. 1676-1689, December 1996.
  2. Taiichi Hamano, Keiichi Tokuda, and Mineo Kaneko, Image Restoration Based on Estimation of Fractal Structure, Proceedings of IEEE Region 10 Conference (TENCON), pp. 311-316, November 1996.
  3. Fernando G. V. Resende, Keiichi Tokuda, Mineo Kaneko and Akinori Nishihara, RLS Algorithms for Adaptive AR Spectrum Analysis Based on Multi-Band Decomposition of The Linear Prediction Error, Proceedings of IEEE Region 10 Conference (TENCON), pp. 541-546, November 1996.
  4. Mineo Kaneko, Hiroyuki Miyauchi and Choon-Sik Park, Link Sharing Scheme for Fault Tolerant Systolic Arrays Based on Mixed Spatial-Temporal Triple Modular Redundancy, Proceedings of IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), pp. 472-475, November 1996.
  5. Fernand G. V. Resende, Paulo S. R. Diniz, Keiichi Tokuda, Mineo Kaneko and Akinori Nishihara, LMS-Based Algorithms with Multi-Band Decomposition of The Linear Prediction Error, Proceedings of IEICE Digital Signal Processing Symposium (DSP Symposium), pp. 379-384, November 1996.
  6. Fernando G. V. Resende, Keiichi Tokuda, and Mineo Kaneko, Adaptive AR Spectrum Estimation Based on Wavelet Decomposition of The Linear Prediction Error, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol. E79-A, No. 5, pp. 665-673, May 1996.
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