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2024 年 †

  1. Yuya Ushioda, Mineo Kaneko, ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits, IEICE Transaction on Fundamentals, Vol.E107-A, No.3, pp.600-609, March 2024.
  2. Yuya Ushioda, Mineo Kaneko, Optimization of Pipeline Schedule for Hardware Efficient Two-Level Adiabatic Logic Circuits, The 25thWorkshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2024), 6 pages, 2024.
  3. Mineo Kaneko, High Level Dapapath Synthesis for Enhanced Timing Tunability, IEICE Technical Report on VLSI Design Technology, VLD2023-101, HWS2023-61, ICD2023-90, pp.12-17, 2024.
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2023 年 †

  1. Yuya Ushioda, Mineo Kaneko, Optimization of Pipelining and Decompute-Insertion for Hardware Efficient Two-Level Adiabatic Logic, IPSJ, Design Automation Symposium, DAS2023, 2023.
  2. Saher Javaid, Mineo Kaneko, Yasuo Tan, A Novel Energy Balancing Considering Periodic Behavior Pattern of Power System, 58th International Universities Power Engineering Conference, 6 pages, 2023.
  3. Saher Javaid, Mineo Kaneko, Yasuo Tan, Supply-Dominated Energy Balancing for Periodic Operation of Power System, Proceedings of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2 pages, 2023.
  4. Akanit Kwangkaew, Siriya Skolthanarat, Chalie Charoenlarpnopparut, Mineo Kaneko, Optimal Location and Sizing of Renewable Distributed Generators forImproving Robust Voltage Stability against Unconstrollable Reactive Compensation, IEEE Access, Vol. 11, pp. 52260-52274, DOI 10.1109/ACCESS.2023.3279716, 2023.
  5. Saher Javaid, Mineo Kaneko, Yasuo Tan, A Case Study on Robust Power/Energy Blancing Driven Cost Optimization for Sizing Energy Storage, Power Generators and Consumers, IEEE 6th International Conference on Energy Conservation and Efficiency, March 2023.
  6. Mineo Kaneko, Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders, Proceedings of IEEE International Symposium on Circuits and Systems, 5 pages, May 2023.
  7. Mineo Kaneko, Skew Tunability Aware High Level Synthesis Considering Resource Binding-Driven Thermal Distribution, IEICE Technical Report on VLSI Design Technology, VLD2022-89, HWS2022-60, pp. 97-102, 2023.
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2022 年 †

  1. Yuya Ushioda, Mineo Kaneko, Hardware Minimization of Two-Level Adiabatic Logic Based on Weighted Maximum Stable Set Problem, Proceedings of 2022 IEEE 40th International Conference on Computer Design (ICCD 2022), pp.394-397, 2022.
  2. Mineo Kaneko, A Study on Co-Optimization of Logical Structure and Bit-line Placement for Parallel Prefix Adders, IEICE Technical Report on VLSI Design Technology, VLD2022-20, pp.7-12, 2022.
  3. Kazuya Uryu, Mineo Kaneko, Co-optimization of Prefix Structure and Bit-Line Arrangement for Long Bit-Length Parallel Prefix Adders, Proceedings of The 24th Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI 2022) , pp.83-84, 2022.
  4. Yuya Ushioda, Mineo Kaneko, An Approach to Hardware Reduction in Adiabatic Logic Circuit based on Maximum Stable Set Problem, IPSJ, Design Automation Symposium, DAS2022, pp.234-241, 2022.
  5. Tomohiro Noguchi, Omran Hindawi, Mineo Kaneko, Three-Dimensional Flexible-Module Placement for Stacked Three-Dimensional Integration, Proceedings of 2022 IEEE International Symposium on Circuits and Systems, pp.3260-3264, 2022.
  6. Saher Javaid, Mineo Kaneko, Yasuo Tan, LP-based Co-optimization of Power Generators and Power Storage Systems under the Condition of Safe Operation, IEEE ICCE-TW, 2022.
  7. Mineo Kaneko, Datapath Synthesis Considering Temperature Dependent Timing Skew, IEICE Technical Report on VLSI Design Technology, VLD2021-79, HWS2021-56, pp.19-24, 2022-03.
  8. Akanit Kwangkaew, Saher Javaid, Chalie Charoenlarpnopparul, Mineo Kaneko, Optimal Location and Sizing of Renewable Distributed Generators Improving Voltage Stability and Security consiering Reactive Power Compensation, MDPI Energies, Volume 15, Issue 6, Article 2126, 23 pages, March 2022.
  9. Saher Javaid, Mineo Kaneko, Yasuo Tan, System Condition for Power Balancing between Fluctuating and Controllable Devices and Optimizing Storage Sizes, MDPI Energies, Vol.15, Article 1055, 2022.
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2021 年 †

  1. Mineo Kaneko, ''Minimum Structural Transformation in Parallel Prefix Adders and Its Application to Search-Based Optimization'', IEEE International Symposium on Circuits and Systems (ISCAS 2021), 5 pages, 2021.
  2. Aye Myat Mon, Mineo Kaneko, Structural Doubling Operations for Efficient Design of Long Bit Length Parallel Prefix Adders, The 23d Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI), 2021.
  3. Mineo Kaneko, Fighting Against Variations for High Performance LSI: Mechanisms and Optimization, IEICE Technical Report on Circuits and Systems, CAS2020-76, CS2020-83, pp.23-28, 2021-03.
  4. Tomohiro Noguchi, Mineo Kaneko, A Fundamental Study on Three-Dimensional Module Placement for Layered Three-Dimensional LSI, IEICE Technical Report on VLSI Design Technology, VLD2020-81, HW2020-56, pp.73-78, 2021-03.
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2020 年 †

  1. Masato Tatsuoka, Mineo Kaneko, High Level Congestion Detection from C/C++ Source Code for High Level Synthesis, IEICE Trans. Foundations, Vol. E103-A, No. 12, pp.1437-1446, December 2020.
  2. Saher Javaid, Mineo Kaneko, Yasuo Tan, An Efficient Testing Scheme for Power-Balanceability of Power System Including Controllable and Fluctuating Power Devices, MDPI Designs, Vol. 4, Issue 4, Article 48 (23 pages) December 2020.
  3. Mineo Kaneko, Insertion-Based Procedural Construction and Optimization of Parallel Prefix Adders, Proceedings of International Symposium on Circuits and Systems (ISCAS), Paper ID 1967, five pages, October 2020 (originally May 2020).
  4. Saher Javaid, Mineo Kaneko, Yasuo Tan, System Condition for Controllable Power Flow Sysem Considering Reaction Delay, IEEE International Conference on Consumer Electronics-Taiwan, 2020.
  5. Akanit Kwangkaew, Saher Javaid, Mineo Kaneko, Chalie Charoenlarpnopparut, A New Approach to Renewable Energy Sources Allocation Considering Robustness against Fluctuations, Proceedings of International Conference on Smart Grids and Energy Systems (SGES), pp.396-401, 2020.
  6. Saher Javaid, Mineo Kaneko, Tasuo Tan, Yuto Lim, Power Flow Management: A Review of Models and Issues, IEICE Technical Report on Information Networks, IN2019-82, pp.37-41, 2020-3.
  7. Saher Javaid, Mineo Kaneko, Yasuo Tan, Structural Condition for Controllable Power Flow System Containing Controllable and Fluctuating Power Devices, Section of Smart Grids and Microgrids, Energies, MDPI, Vol.13, No.1627; doi:10.3390/en13071627, 20 pages, April 2020.
  8. Mineo Kaneko, Two-Graph Approach to Temperature Dependent Skew Scheduling, Proceedings of International Symposium on Quality Electronic Design (ISQED), pp.432-437, March 2020.
  9. Mineo Kaneko, Thermal-Aware Clock Skew Scheduling Based on Two-Graph Approach, IEICE Technical Report on VLSI Design Technology, VLD2019-104, HWS2019-77, pp.59-64, March 2020.
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2019 年 †

  1. Saher Javaid, Mineo Kaneko, Yasuo Tan, Robustness Test Method of Power Flow System Containing Controllable and Fluctuating Power Devices, 11th IEEE Asia-Pacific Power and Energy Engineering Conference, December 2019.
  2. Saher Javaid, Mineo Kaneko, Yasuo Tan, Power Flow Management: Solvability Condition for a System with Controllable and Fluctuating Devices, 11th IEEE Asia-Pacific Power and Energy Engineering Conference, December 2019.
  3. Yuta Hiyama, Takayuki Todokoro, Kenshu Seto, Masato Tatsuoka, Yoshihito Nishida, Mineo Kaneko, High-Level Synthesis Code Optimization with Loop Fusion based on LLVM/Polly, The 22nd Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI 2019), pp.208-213, October 2019.
  4. Bo-Yu Tseng, Mineo Kaneko, Insertion Based Procedural Construction of Parallel Prefix Adders, The 22nd Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI 2019), pp.83-88, October 2019. (Outstanding Paper Award)
  5. Saher Javaid, Mineo Kaneko, Yasuo Tan, A Linear Programming Model for Power Flow Control Problem Considering Controllable and Fluctuating Power Devices, 2019 IEEE 8th Global Conference on Consumer Electronics, October 2019.
  6. Saher Javaid, Mineo Kaneko, Yasuo Tan, Power Flow Management for Smart Grids: Considering Renewable Energy and Demand Uncertainty, 2019 IEEE International Conference on Consumer Electronics -- Taiwan (IEEE ICCE-TW), two-pages, May 2019.
  7. Mineo Kaneko, A Novel Framework for Procedural Construction of Parallel Prefix Adders, Proceedings of 2019 IEEE International Symposium on Circuits and Systems, five pages, May 2019.
  8. Mineo Kaneko, Optimization of Parallel Prefix Adder Structure Generated by Insertion Operations, IEICE Technical Report on Circuits and Systems, CAS2019-48, pp.21-26, 2019.
  9. Mineo Kaneko, Procedural Construction of Parallel Prefix Adder by Insertion Operation, DA Symbosium 2019, IPSJ, pp.136-141, 2019.
  10. Mineo Kaneko, Timing Correction by Constrained Temperature Dependent Clock Skew, IEICE Technical Report on VLSI Design Technology, VLD2018-2013, HWS2018-66, pp.61-66, 2019.
  11. Masato Tatsuoka, Mineo Kaneko, Pattern Matching Based Detection of Wire Congestion from Source Code Description for High Level Synthesis, IEICE Technical Report on VLSI Design Technology, VLD2018-96, HWS2018-59, pp.19-24, 2019.
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2018 年 †

  1. Mineo Kaneko, Procedural Construction of Parallel Prefix Adder, DA Symbosium 2018, IPSJ', pp.197-202, 2018.
  2. Masato Tatsuoka, Mineo Kaneko, Wire Congestion Aware High Level Synthesis Flow with Source Code Complier,'' Proceedings of IEEE International Conference on IC Design and Technology, pp.101-104, June 2018.
  3. Takayuki Moto, Mineo Kaneko, Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing, Proceedings of IEEE International Symposium on Circuits and Systems, five pages, May 2018.
  4. Kazuho Katsumata, Junghoon Oh, Mineo Kaneko, Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability, Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2018), pp.232-237, 2018.
  5. Tatsuhiro Nishioka, Mineo Kaneko, Design Optimization of Parallel Prefix Adder Considering Buffer Insertion, IEICE Technical Report on VLSI Design Technology, VLD2017-109, pp.121-126, 2018.
  6. Junghoon Oh, Mineo Kaneko, Reliability Evaluation of Mixed Error Correction Scheme for Soft-Error Tolerant Datapaths, IEICE Technical Report on VLSI Design Technology, VLD2017-102, pp.79-84, 2018.
  7. Cheng Ma, Mineo Kaneko, Reconfiguration for Fault Tolerant FPGA Considering Incremental Multiple Faults, IEICE Technical Report on VLSI Design Technology, VLD2017-101, pp.73-78, 2018.
  8. Masato Tatsuoka, Mineo Kaneko, Congestion Aware High Level Synthesis Design Flow with Source Compiler, IEICE Technical Report on VLSI Design Technology, VLD2017-96, pp.43-48, 2018.
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2017 †

  1. Mineo Kaneko, A General Model of Timing Correction by Temperature Dependent Clock Skew, IEICE Technical Report on VLSI Design Technology, VLD2017-57, DC2017-63, pp.183-188, November 2017.
  2. Masato Tatsuoka, Junghoon Oh, Mineo Kaneko, High Level Synthesis Design Flow with Source Compiler Based on LLVM, DA Symbosium 2017, IPSJ, August 2017.
  3. Renyuan Zhang, Mineo Kaneko,A Random Access Analog Memory with Master-Slave Structure for Implementing Hexadecimal Logic, IEEE International System-On-Chip Conference (SOCC) 2017, pp.7-11, 2017.
  4. Mineo Kaneko,Margin Aware Timing Test and Tuning Algorithm for Post-Silicon Skew Tuning, '''2017 IEEE 60th International Widwest Symposium on Circuits and Systems (MWSCAS 2017)''', pp.1244-1247, August, 2017.
  5. Junghoon Oh, Mineo Kaneko, Latency-Aware Selection of Check Variables for Soft-Error Tolerant Datapath Synthesis, IEICE Trans. Foundations, Vol.E100-A, No.7, pp.1506-1510, July 2017.
  6. Mineo Kaneko, KKT-Condition Inspired Solution of DVFS with Limited Number of Voltage Levels, Proceedings of International Symposium on Circuits and Systems (ISCAS) 2017, pp.2400-2403, May, 2017.
  7. Xiaoguang Li, Mineo Kaneko, Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis, IEICE Technical Report on VLSI Design Technology, VLD2016-118, pp.85-90 March 2017.
  8. Makoto Soga, Mineo Kaneko, Optimum Temperature Dependent Timing Skew for Temperature Aware Design, IEICE Technical Report on VLSI Design Technology, VLD2016-119, pp.91-96 March 2017.
  9. Kai Shimura, Mineo Kaneko, MILP Approach to Skew-Aware High Level Synthesis, IEICE Technical Report on VLSI Design Technology, VLD2016-120, pp.97-102 March 2017.
  10. Takayuki Moto, Mineo Kaneko, Optimization of Parallel Prefix Adder Using Simulated Annealing, IEICE Technical Report on VLSI Design Technology, VLD2016-127, pp.139-144 March 2017.
  11. Junghoon Oh, Mineo Kaneko, Effect on the Chip Area of Component Adjacency Constraint for Soft-Error Tolerant Datapaths, IEICE Technical Report on VLSI Design Technology, VLD2016-129, pp.151-156 March 2017.
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2016 †

  1. Junghoon Oh, Mineo Kaneko, Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing, IEICE Trans. Fundations, Vol.E99-A, No.7, pp.1311-1322, July 2016.
  2. Renyuan Zhang, Mineo Kaneko, A 16-Valued Logic FPGA Architecture Employing Analog Memory Circuit, Proc. IEEE International Symposium on Circuits and Systems, pp. 718-721, (May 2016).
  3. Junghoon Oh, Mineo Kaneko, Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.595-600, July 2016 (Pittsburgh, Pennsylvania, USA).
  4. Junghoon Oh, Mineo Kaneko, Mixed Error Correction Scheme and Its Design Optimization for Soft-Error Tolerant Datapaths, Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp.362-365, October 2016 (Korea) .
  5. Mineo Kaneko, KKT-Condition Based Study on DVFS for Heterogeneous Task Set, Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp.717-720, October 2016 (Korea).
  6. Keisuke Inoue, Mineo Kaneko, MILP-based Scheduling for Clock Latency Minimization in High-level Synthesis, Proc. 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2016), pp.925-928, July 2016 (Okinawa).
  7. Makoto Soga, Mineo Kaneko, Optimization of Temperature Dependent Intentional Skew for Temperature Aware Timing Design, Proceedings of 20th Workshop on Synthesis and System Integration of Mixed Information Technologies, pp.119-124, October, 2016 (Kyoto).
  8. Renyuan Zhang, Mineo Kaneko, A Feasibility Study of Master-Slave Flipflop Design for Hexadecimal Logic, IEEE Industrial Electronics and Applications Conference, November, 2016.
  9. Mineo Kaneko, A Study on Multi-Level DVFS for Heterogeneous Task Set, Proc. of Design Automation Symposium, IPSJ, pp.146-150, September 2016.
  10. Kazuho Katsumata, Mineo Kaneko, Resource Binding in Datapath Synthesis for Performance Enhancement by Post-Silicon Skew Tuning, IEICE Technical Report on VLD, VLD2015-141, pp.173-178, February 2016.
  11. Keisuke Inoue, Mineo Kaneko, A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis,, IEICE Technical Report on VLD, VLD2015-117, pp. 37-42, February 2016.
  12. Junghoon Oh, Mineo Kaneko, ILP Based Synthesis of Soft-Error Tolerant Datapaths Considering Adjacency Constraint between Components, IEICE Technical Report on VLD, VLD2015-116, pp.31-36, February 2016.
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2015 †

  1. Junghoon Oh, Mineo Kaneko, An Approach to Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components, IEICE Technical Report on VLD, VLD2015-62, pp.159-164, December 2015.
  2. Mineo Kaneko, A Study on DVFS for Heterogeneous Task Set, IEICE Technical Report on VLD, VLD2015-47, pp. 63-68, December 2015.
  3. Renyuan Zhang, Mineo Kaneko, Robust and Low-Power Digitally-Programmable-Delay-Element Designs Employing Neuron-MOS Mechanism, ACM Transactions on Design Automation of Electronic Systems, Vol. 20, No. 4, Article 64 (19 pages), September 2015.
  4. Keisuke Inoue, Mineo Kaneko, Bitwidth-Aware Register Allocation and Binding for Clock Period Minimization, Proc. IEEE 58th International Midwest Symposium on Circuits and Systems, pp.499-502, August 2015.
  5. Renyuan Zhang, Mineo Kaneko, A Feasibility Study of Quaternary FPGA Designs by Implementing Neuron-MOS Mechanism, Proc. IEEE International Symposium on Circuits and Systems, pp. 942-945, May 2015.
  6. Junghoon Oh, Mineo Kaneko, Automated Selection of Check Variables for Area-Efficient Soft-Error Tolerant Datapath Synthesis, Proc. IEEE International Symposium on Circuits and Systems, pp.49-52, May 2015.
  7. Mineo Kaneko, A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling, Proceedings of ACM Great Lakes Symposium on VLSI, pp.367-372, May 2015.
  8. Junghoon Oh, Mineo Kaneko, Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing in Triple Algorithm Redundancy, Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), pp.272-277, March 2015.
  9. Renyuan Zhang, Mineo Kaneko, A Quaternary Master-Slave Flip-Flop with Multiple Functions for Multi-Valued Logics, Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), pp.193-198, March 2015.
  10. Junghoon Oh, Mineo Kaneko, ILP Based Synthesis for Area-Efficient Soft-Error Tolerant Datapaths, IEICE Technical report on VLD, VLD2014-164, pp.67-72, March 2015.
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2014 †

  1. Renyuan Zhang, Mineo Kaneko, A Temperature and Process Variation Insensitive PDE Circuit Employing Neuron-MOS, IEEE/ACM Workshop on Variability Modeling and Characterization (VMC) 2014, November 2014.
  2. Mineo Kaneko, Timing-Test Scheduling for PDE Tuning Considering Multiple-Path Testability, IEICE Technical report on VLD, VLD2014-94, DC2014-48, pp.149-154, November 2014.
  3. Mineo Kaneko, Yutaka Tsuboishi, Constrained Binding and Scheduling of Triplicated Algorithm for Fault Tolerant Datapath Synthesis, Proceedings of IEEE International Symposium on Circuits and Systems, pp.1448-1451, June 2014.
  4. H. Nishiyama, M. Inagi, S. Wakabayashi, S. Nagayama, K. Inoue, M. Kaneko, An ILP-based Optimal Circuit Mapping Method for PLDs, Proceedings of IEEE Reconfigurable Architectures Workshop (RAW 2014), pp.-, May 2014.
  5. Renyuan Zhang, Mineo Kaneko, A Feasible Study on Robust Programmable Delay Element Design Based on Neuron-MOS Mechanism, Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp.21-26, May 2014.
  6. Mineo Kaneko, Scheduling of PDE Setting and Timing Tests for Post-Silicon Skew Tuning with Timing Margin [Extended Abstract], Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp.91-92, May 2014.
  7. Junghoon Oh, Mineo Kaneko, Area-Efficient Soft-Error Tolerant Datapath Design Based on Aggressive Resource Sharing, IEICE Technical report on VLD, VLD2013-156, pp.119-124, March 2014.
  8. Tatsunori Kubo, Mineo Kaneko, Post-Silicon Tuning of Body Biasing and Clock Skew for Low-Voltage LSI, IEICE Technical report on VLD, VLD2014-163, pp.159-163, March 2014.
  9. Kotaro Kato, Mineo Kaneko, A Design Method of Mixed Synchronous-Asynchronous Circuit, IEICE Technical report on VLD, VLD2013-164, pp.165-170, March 2014.
  10. Masato Tatsuoka, Toshiaki Aoki, and Mineo Kaneko, Function Code Extraction from RTL Property for Reuse, IEICE Technical report on VLD, VLD2013-165, pp.171-176 March 2014.
  11. Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim, System Design and Analysis for Maximum Consuming Power Control in Smart House, Journal of Automation and Control Engineering, Engineering and Technology Publishing, Vol. 2, No. 1, pp.43-48, March 2014 issue (October 2013 On-line publication).
  12. Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim, Priority Based Maximum Consuming Power Control in Smart Homes, 5th Innovative Smart Grid Technologies Conference, February 2014.
  13. Renyuan Zhang, Mineo Kaneko, A Feasible Study of Robust and Low-Power Programmable Delay Elements Based on Neuron-MOS Mechanism, Papers of Technical Meeting on Electronic Circuits, IEE Japan, No.ECT-14-15, pp.75-80, January 2014.
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2013 †

  1. Keisuke Inoue and Mineo Kaneko, Dual-edge-triggered Flip-flop-based High-level Synthesis with Programmable Duty Cycle, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol.E96-A, No.12, pp.2689-2697, December 2013.
  2. Mineo Kaneko, Scheduling of PDE Setting and Timing Test for Post Silicon Skew Tuning, IEICE Technical Report, VLD2013-98, DC2013-64, pp.269-274, November 2013.
  3. Renyuan Zhang, Mineo Kaneko, Tadashi Shibata, A Fully-Parallel Self-Learning Analog Support Vector Machine Employing Compact Gaussian-Generation Circuit, Proceedings of International Conference on Solid-State Devices and Materials, pp.174-175, September 2013.
  4. Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim, System Design and Analysis for Maximum Consuming Power Control in Smart House, International Conference on Power and Energy Engineering, September 2013.
  5. Keisuke Inoue and Mineo Kaneko, Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-flops and Latches, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol.E96-A, No.8, pp.1712-1722, August 2013.
  6. Masato Tatsuoka, Mineo Kaneko, High Level Resynthesis Apparoch of Reusable RTL Property, IEICE Technical Report, VLD2012-145, pp.55-60, March 2013.
  7. Mineo Kaneko, Test Planning for Post-Silicon Skew Tuning Based on Graph Partitioning, IEICE Technical Report, VLD2012-159, pp.129-133, March 2013.
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2012 †

  1. Keisuke Inoue and Mineo Kaneko, A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-skew Tolerant Datapaths, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol.E95-A, No.12, pp.2330-2337, December 2012.
  2. Mineo Kaneko, Dynamic Timing-Test Scheduling for Post-Silicon Skew Tuning, IEICE Technical Report, VLD2012-85, DC2012-51, pp.153-158, November 2012.
  3. Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim, Energy Stability-aware Scheme for Intelligent Home Energy Management Systems, IPSJ SIG Technical Report, Vol. 2012-MBL-64, No.21, pp.1-6, November 2012.
  4. Mineo Kaneko, Timing-Test Scheduling for Constraint-Graph Based Post-Silicon Skew Tuning, Proceedings of IEEE International Conference on Computer Design (ICCD), pp.460-465, October 2012.
  5. Keisuke Inoue and Mineo Kaneko, Statistical Timing-Yield Driven Scheduling and FU Binding in Latch-Based Datapath Synthesis, Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp.631-634, August 2012.
  6. Mineo Kaneko and Li Jian, Post-Silicon Skew Tuning Algorithm Utilizing Setup and Hold Timing Tests, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp.125-128, May 2012.
  7. Keisuke Inoue and Mineo Kaneko, Reliable and Low-Power Clock Distribution Using Pre- and Post-Silicon Delay Adaptation in High-Level Synthesis, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp.1664-1667, May 2012.
  8. Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, and Hafiz Md. Hasan Babu, An Efficient Approach for Designing and Minimizing Reversible Programmable Logic Arrays, Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp.215-220, May 2012.
  9. Keisuke Inoue and Mineo Kaneko, Optimal Register-Type Selection during Resource Binding in Flip-Flop/Latch-Based High-Level Synthesis, Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp.79-82, May 2012.
  10. Keisuke Inoue and Mineo Kaneko, Register Binding and Domain Assignment for Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis, Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp.778-783, March 2012.
  11. Yousuke Haruta and Mineo Kaneko, Resource Binding for Datapaths with Improved Post-Silicon Skew Tunability, IEICE Technical Report (VLD), March 2012.
  12. Keisuke Inoue and Mineo Kaneko, Performance-Driven Register Write Inhibition in High-Level Synthesis under Strict Maximum-Permissible Clock Latency Range, IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 239-244, January 2012.
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2011 †

  1. Tsuyoshi Iwagaki, Eiri Takeda, and Mineo Kaneko, Flexible Test Scheduling for an Asynchronous On-chip Interconnect through Special Data Transfer, IEICE Trans. on Fundamentals, vol. E94-A, no. 12, pp. 2563-2570, December 2011.
  2. Mineo Kaneko, A Basic Study on Timing-Test Scheduling for Post-Silicon Skew Tuning, IEICE Technical Report (VLD), November 2011.
  3. Keisuke Inoue and Mineo Kaneko, Early Planning for RT-Level Delay Insertion during Clock Skew-Aware Register Binding, Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp.154-159, October 2011.
  4. Keisuke Inoue and Mineo Kaneko, Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis, IEICE Technical Report (VLD), pp.61-66, September 2011.
  5. Keisuke Inoue and Mineo Kaneko, On the NP-Hardness of Minimum-Period Register Binding, The IEICE 2011 Engineering Sciences Society Conference, A-1-15, September 2011.
  6. Jian Li and Mineo Kaneko, PDE Adjustment Algorithm for Post Silicon Skew Tuning, The IEICE 2011 Engineering Sciences Society Conference, A-3-17, September 2011.
  7. Keisuke Inoue and Mineo Kaneko, Framework for Latch-Based High-Level Synthesis using Minimum-Delay Compensation, IPSJ Transactions on System LSI Design Methodology (TSLDM), vol. 4, pp.232-244, August 2011.
  8. Keisuke Inoue and Mineo Kaneko, Operation Scheduling Considering Time Borrowing for High-Performance Latch-Based Circuits, Proceedings of IEEE International NEWCAS Conference (NEWCAS), pp.245-248, June 2011.
  9. Tsuyoshi Iwagaki and Kewal K. Saluja, Power-Constrained Test Generation for Hold-Time Faults Using Integer Linear Programming, Proceedings of IEEE International Workshop on the Impact of Low Power design on Test and Reliability (LPonTR), accepted as lecture, May 2011.
  10. Keisuke Inoue and Mineo Kaneko, Variable-Duty-Cycle Scheduling in Double-Edge-Triggered Flip-Flop-Based High-Level Synthesis, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp.550-553, May 2011.
  11. Mineo Kaneko and Keisuke Inoue, Ordered Coloring-Based Resource Binding for Datapaths with Improved Skew-Adjustability, Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp.307-312, May 2011.
  12. Tsuyoshi Iwagaki and Kewal K. Saluja, Indirect Detection of Clock Skew Induced Hold-Time Violations on Functional Paths Using Scan Shift Operations, Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp.175-178, April 2011.
  13. Keisuke Inoue, Mineo Kaneko, and Tsuyoshi Iwagaki, Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, vol.E94-A, no.4, pp.1067-1081, April 2011.
  14. Mineo Kaneko, A Complete Framework of Simultaneous Functional Unit and Register Binding with Skew Scheduling, Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp.189-195, March 2011.
  15. Tsuyoshi Iwagaki and Kewal K. Saluja, On Indirect Detection of Functional Hold-Time Violations Using Scan Shift Operations,IEICE Technical Report (FIIS),FIIS-11-298, pp.1-5, March 2011.
  16. Shuichi Sowa and Mineo Kaneko, Low Power Design of Digital Circuits using Quasi-complementary MOS Gates, IEICE Technical Report (VLD), VLD2010-122, pp.37-42, March 2011.
  17. Dang Yu and Mineo Kaneko, Delay Variation-Aware Datapath Synthesis for Improved Performance and Tunability, IEICE Technical Report (VLD), VLD2010-133, pp.99-104, March 2011.
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2010 †

  1. K. Inoue and M. Kaneko, "Optimal register assignment with minimum-delay compensation for latch-based design," Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 887-890, December 2010.
  2. Tsuyoshi Iwagaki, Eiri Takeda and Mineo Kaneko, "An approach to test scheduling for asynchronous on-chip interconnects using integer programming," Digest of Papers 11th IEEE Workshop on RTL and High Level Testing (WRTLT '10), pp. 69-74, Dec. 2010.
  3. Mineo Kaneko, ``ILP Approach to Extended Ordered Coloring for Skew Ajdustability-Aware Resource Binding'', IEICE Tech. Rep. VLD2010-75, DC2010-42, pp.131-136, Dec. 2010
  4. K. Inoue and M. Kaneko, "A novel IR-drop tolerant scheduling for reliability-aware datapaths," Proc. Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 76-81, October 2010.
  5. Mineo Kaneko, Takayuki Shibata, ``Extended Sequence Pair: A Finite Solution Space for Two-Directional Repeated Placement'', The 16th Workshop on Synthesis And System Integration of Mixed Information technology (SASIMI2010), pp. 190--195, October 2010
  6. Mineo Kaneko, ``Ordered Coloring for Skew Adjustability-Aware Resource Binding'', IEICE Tech. Rep. VLS2010-42, pp.1--6, Sept. 2010
  7. K. Inoue and M. Kaneko, "Adjustable safe clocking-based register assignment considering the setup and hold timing constraints," Proc. IPSJ DA Symposium, pp. 81-86, September 2010.
  8. K. Inoue and M. Kaneko, "Minimizing clocking patterns of adjustable safe clocking for timing variation-aware datapaths," Proc.IEEE Mid-West Symposium on Circuits and Systems (MWSCAS), pp. 113-116, August 2010.
  9. K. Inoue and M. Kaneko, "Clocking pattern minimization for adjustable safe clocking-based register assignment," Proc. IEICE Technical Report, vol. 110, no. 86, pp. 1-6, June 2010.
  10. Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko, ``Test Scheduling Algorithms for Delay-Insensitive Chip Area Interconnects Based on Cone Partitioning'', Proceedings of 3'rd International Workship on the Impact of Low-Power Design on Test and Reliability (LPonTR 2010), 2 pages (May 2010) (at Czech Republic)
  11. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, ``A Novel Resource Sharing Model and High-Level Synthesis for Delay Variability-Tolerant Datapaths'', Proceedings of ACM Great Lake Symposium on VLSI, pp.111-114 (May 2010)
  12. Tsuyoshi Iwagaki, Mineo Kaneko, ``A Psuedo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties'', Proceedings of IEEE International Sumposium on Electornic Design, Test and Applications (DELTA2010), pp.293-296 (January 2010)
↑

2009 †

  1. Tsuyoshi Iwagaki, Mineo Kaneko, ``A Heuristic Approach to Detecting Transition Faults at All Circuit Outputs'', Proc. IEICE Society Conference, p. 54, Sep. 2009.
  2. Keisuke Inoue, Mineo Kaneko, ``Complete ILP Formulation of High-Level Synthesis'', IEICE Technical Report, VLD2009-32, pp.19-24 (September 2009)
  3. Keisuke Inoue, Takayuki Obata, Yayumi Uehara, Mineo Kaneko, ``Optimal Stall Insertion with Timing Skew Adjustment for Tunable LSIs'', Proceedings of IEEE International Midwest Symposium on Circuits and Systems, pp.1187-1190 (August, 2009)
  4. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, ``Resource Sharing and Scheduling Algorithms against Variation of Control Timings'', IEICE Technical report, CAS2009-5, VLD2009-10, SIP2009-22, pp.25-30 (July 2009)
  5. Takayuki Obata and Mineo Kaneko, ``Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis,'' Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS2009), pp. 1521-1524, May 2009.
  6. Keisuke Inoue, Mineo Kaneko and Tsuyoshi Iwagaki, ``Safe Clocking for the Setup and Hold Timing Constraints in Datapath Synthesis,'' Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI2009), pp.27-32, May 2009.
  7. Keisuke Inoue, Mineo Kaneko and Tsuyoshi Iwagaki, ``Safe Clocking Based Datapath Synthesis for the Setup and Hold Timing Constraints,'' IEICE Circuits and Systems KARUIZAWA Workshop, pp. 432-437, Apr. 2009.
  8. Keisuke Inoue, Mineo Kaneko and Tsuyoshi Iwagaki, ``Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths,'' IEICE Trans. Fundamentals, Vol.E92-A, No.4, pp. 1096-1105, Apr. 2009.
  9. Keisuke Inoue and Mineo Kaneko, ``A Note on the NP-completeness of the Ordered Coloring on Unit Interval Graphs,'' IEICE General Conference, No.A-1-16, p. 16. Mar. 2009.
  10. Keisuke Inoue, Mineo Kaneko and Tsuyoshi Iwagaki, ``Adjustable Safe Clocking and Relevant Register Assignment in Datapath Synthesis,'' IEICE Technical Report, VLD2008-130, pp.23-28, Mar. 2009.
  11. Tsuyoshi Iwagaki and Mineo Kaneko, ``On the Derivation of a Minimum Test Set in High Quality Transition Testing,'' Proc. IEEE Latin-American Test Workshop, pp. 1-6, Mar. 2009.
  12. Keisuke Inoue, Mineo Kaneko and Tsuyoshi Iwagaki, ``A Conjecture on the Number of Extra Registers in Safe Clocking-Based Register Assignment,'' The 15th Workshop on Synthesis And System Integration of Mixed Information technology (SASIMI2009), pp. 131-136, Mar. 2009.
  13. Keisuke Inoue, Mineo Kaneko and Tsuyoshi Iwagaki, ``A Note on the Number of Extra Registers in Safe Clocking-Based Register Assignment,'' IEICE Technical Report, CAS-2008-90, NLP2008-120 pp. 147-152, Jan. 2009.
↑

2008 †

  1. Takayuki Obata, Mineo Kaneko, ``Simultaneous Optimization of Skew and Control Step Assignment in RT-Datapath Synthesis,'' IEICE Trans. Fundamentals, Vol. E91-A, No. 12, pp.3585-3595, Dec. 2008.
  2. Keisuke Inoue, Mineo Kaneko and Tsuyoshi Iwagaki, ``Delay variability-aware datapath synthesis based on safe clocking for setup and hold timing constraints,'' IEICE Technical Report, VLD2008-85, pp. 151-156, Nov. 2008.
  3. Tsuyoshi Iwagaki and Mineo Kaneko, ``An integer programming formulation for generating high quality transition tests,'' IEICE Technical Report, DC2008-29, pp. 7-12, Nov. 2008.
  4. Keisuke Inoue, Mineo Kaneko and Tsuyoshi Iwagaki, ``Safe Clocking Register Assignment in Datapath Synthesis,'' Proceedings of IEEE International Conference on Computer Design, pp. 120-127, Oct. 2008.
  5. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, ``Delay Variation-Aware Datapath Synthesis Based on Register Clustering,'' IEICE Technical Report, VLD2008-51, pp. 25-30, Sep. 2008.
  6. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, ``Minimizing Minimum Delay Compensations for Timing Variation-Aware Datapaths Synthesis,'' Proceedings of IEEE Midwest Symposium on Circuits and Systems, pp. 97-100, Aug. 2008.
  7. Takayuki Obata, and Mineo Kaneko, ``Concurrent Skew and Control Step Assignments in RT-Level Datapath Synthesis,'' Proceedings of IEEE International Symposium on Circuits and Systems, pp. 2018-2021, May 2008.
  8. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, ``Novel Register Sharing in Datapath for Structural Robustness against Delay Variation,'' IEICE Trans. Fundamentals, Vol. E91-A, No. 4, pp. 1044-1053, Apr. 2008.
↑

2007 †

  1. Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara, ``Efficient Path Delay Test Generation Based on Stuck-at Test Generation Using Checker Circuitry,'' Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 418-423, Nov. 2007.
  2. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki, ``Structural Robustness of Datapaths against Delay-Variations,'' Proceedings of the 14th Workshop on Synthesis and System Integration of Mixed Information technology (SASIMI2007), pp. 272-279 , Oct. 2007.
  3. Yuuki Yano, Mineo Kaneko, ``Solution Space Reduction of Sequence Pairs using Model Placement,'' Proceedings of IEEE Midwest Symposium on Circuits and Systems 2007, pp. 1130-1133, Aug. 2007.
  4. Khin Thida Latt, Mineo Kaneko, Yoichi Shinoda, ``Parallel Computation of Data Summation for Multiple Problem Spaces on Partitioned Optical Passive Stars Network,'' International Journal of Electronics, Circuits and Systems, Vol. 1, No. 2, pp. 110-115, June 2007.
  5. Khin Thida Latt, Mineo Kaneko, Yoichi Shinoda, ``Parallel Computation of Data Summation for Multiple Problem Spaces on Partitioned Optical Passive Stars Network,'' International Conference on Parallel and Distributed Computing Systems, May 2007.
  6. Koji Ohashi and Mineo Kaneko, "Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath," Proc. ACM Great Lakes Symposium on VLSI, pp. 481-484, Mar. 2007.
  7. Koji Ohashi and Mineo Kaneko, "Statistical analysis driven synthesis of application specific asynchronous systems," IEICE Transactions on Fundamentals, Vol. E90-A, No.3, pp.659-669, Mar. 2007
  8. Koji Ohashi and Mineo Kaneko, "Loop pipeline scheduling for assignment constrained iteration period minimization," WSEAS Transactions on Circuits and Systems, Vol. 6, No. 3, pp.389-396, Mar. 2007
  9. Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko and Hideo Fujiwara, "A test generation framework using checker circuits and its application to path delay test generation," IEICE Technical Report (CAS2006-76), Vol. 106, No. 512, pp.37-42, Jan. 2007.
  10. Takayuki Obata and Mineo Kaneko, "Computational complexity of simultaneous optimization of skew, schedule and clock in high-level synthesis," IEICE Technical Report (CAS2006-75), Vol. 106, No. 512, pp. 31-36, Jan. 2007.
↑

2006 †

  1. Mineo Kaneko, "Minimal set of essential resource disjoint pairs for exploring feasible 3D schedules," Proc. IEEE Asia-Pacific Conference on Circuits and Systems, pp. 335-338, Dec. 2006.
  2. Takayuki Obata and Mineo Kaneko, "Computational complexity of simultaneous optimization of control schedule and skew in datapath synthesis," IEICE Techinical Report (VLD2006-65), Nov. 2006. Mineo Kaneko, "Statistical property and subclass structure of sequence triple code space for repeated placements," Proc. IEEE International Midwest Symposium on Circuits and Systems, Aug. 2006.
  3. Koji Ohashi and Mineo Kaneko, "Analysis and optimization of statistical performance for asynchronous datapaths, WSEAS Transactions on Circuits and Systems, Vol. 5, No. 7, pp. 895-902, July 2006.
  4. Koji Ohashi and Mineo Kaneko, "Statistical makespan analysis in asynchronous datapath synthesis," Proc. 10th WSEAS International Conference on Circuits, pp. 318-323, July 2006.
  5. Koji Ohashi and Mineo Kaneko, "Dual-rail two-phase asynchronous datapath synthesis based on aggressive register sharing model," Proc. 19th Workshop on Circuits and Systems in Karuizawa, pp. 589-594, Apr. 2006.
  6. Takayuki Obata and Mineo Kaneko, "Simultaneous control-step and skew assignment for control signals in RT-level datapath synthesis," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 314-321, Apr. 2006.
  7. Mineo Kaneko, "Solution space reduction of sequence pairs using model placement," IEICE Technical Report (CAD2006-5), pp. 25-28, June 2006.
  8. Koji Ohashi and Mineo Kaneko, "Resource sharing in dual-rail two-phase asynchronous datapath synthesis," Technical Report of IEICE (CAS2005-93), Vol. 105, No. 504, pp. 37-42, Jan. 2006.
  9. Takayuki Obata and Mineo Kaneko, "Simultaneous control-step and skew assignment for control signals in RT-level datapath synthesis," Technical Report of IEICE (CAS2005-92), Vol. 105, No. 504, pp. 31-36, Jan. 2006.
↑

2005 †

  1. Mineo Kaneko, "Minimal set of essential lifetime overlaps for exploring 3D schedule," Technical Report of IEICE (VLD2005-64), Vol. 105, No. 442, pp. 19-24, Dec. 2005.
  2. Koji Ohashi and Mineo Kaneko, "Statistical analysis driven synthesis of asynchronous systems," Proc. IEEE International Conference on Computer Design, pp. 200-205, Oct. 2005.
  3. Mineo Kaneko, "Sequence triple: a finite solution space for repeated placement," Proc. IEEE International Midwest Symposium on Circuits and Systems, pp. 1446-1449, Aug. 2005.
  4. Takayuki Obata and Mineo Kaneko, "Control signal skew scheduling in RT level datapath synthesis," Proc. IEEE International Midwest Symposium on Circuits and Systems, pp. 1087-1090, Aug. 2005.
  5. Koji Ohashi and Mineo Kaneko, "Statistical schedule length analysis in asynchronous datapath synthesis," Proc. IEEE International Symposium on Circuits and Systems, pp. 700-703, May 2005.
  6. Koji Ohashi and Mineo Kaneko, "Simultaneous scheduling and binding for asynchronous system with statistical makespan analysis," Proc. 18th Workshop on Circuits and Systems in Karuizawa, pp. 587-592, Apr. 2005.
  7. Takayuki Obata and Mineo Kaneko, "Control signal skew scheduling for RT level datapaths," Proc. 18th Workshop on Circuits and Systems in Karuizawa, pp. 521-526, Apr. 2005.
  8. Takayuki Obata and Mineo Kaneko, "Control signal skew scheduling for RT level datapaths," Technical Report of IEICE (CPSY2004-107), pp. 13-17, Mar. 2005.
  9. Koji Ohashi and Mineo Kaneko, "Statistical schedule length analysis in asynchronous datapath synthesis," Technical Report of IEICE (CAS2004-72), Vol. 104, No. 557, pp. 1-5, Jan. 2005.
  10. Mineo Kaneko and Tomoyuki Ogawa, "A finite solution space for recurrent placements," Technical Report of IEICE (CAS2004-73), Vol. 104, No. 557, pp. 7-12, Jan. 2005.
  11. Takayuki Obata and Mineo Kaneko, "Simultaneous Scheduling and Skew Assignment for Multiplexer Control in Placed Datapaths," Technical Report of IEICE (CAS2004-74), Vol.104, No.557, pp. 13-18, Jan. 2005.
↑

2004 †

  1. Mineo Kaneko and Koji Ohashi, "Assignment constrained scheduling under max/min logic/interconnect delays for placed datapath," Proc. IEEE Asia-Pacific Conference on Circuits and Systems, Vol. 1, pp. 545-548, Dec. 2004.
  2. Koji Ohashi and Mineo Kaneko, "Asynchronous Datapath Synthesis Enhancing Graceful Degradation for Delay Faults," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 303-309, Oct. 2004.
  3. Koji Ohashi and Mineo Kaneko, "Asynchronous Datapath Synthesis Based on Binding Space Exploration," Proc. 17th Workshop on Circuits and Systems in Karuizawa, pp. 49-554, Apr. 2004.
↑

2003 †

  1. Mineo Kaneko and Kazuaki Oshio, "Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism," Proc. International Symposium on Circuits and Systems, Vol. V, pp. 645-648, May 2003.
  2. Takayuki Obata, Mineo Kaneko and Satoshi Tayu, "Automatic register-toregister transfer insertion in assignment driven scheduling," Technical Report of IEICE (VLD2003-2), Vol. 103, No. 40, pp. 7-12, May 2003. (In Japanese)
  3. Yoshihiko Atsumi, Koji Ohashi and Mineo Kaneko, "Local similarity in computation algorithm and its application to data-path synthesis," Technical Report of IEICE (VLD2003-3), Vol. 103, No. 40, pp. 13-18, May 2003. (In Japanese)
  4. Koji Ohashi and Mineo Kaneko, "Binding constrained scheduling for iterative algorithm with conditional branches," Proc. Workshop on Synthesis and System Integration of Mixed Information technology, pp. 144-151, Apr. 2003.
  5. Mineo Kaneko and Koji Ohashi, "Post-floorplan control schedule under max/min logic/interconnect delays," Proc. 16th Workshop on Circuits and Systems in Karuizawa, pp. 195-200, Apr. 2003.
  6. Masahiro Obara, Yasuhiro Takashima and Mineo Kaneko, "Force-directed floorplan synthesis with rearrangement of hierarchical structure," Technical Report of IEICE (VLD2002-148), Vol. 102, No. 683. pp. 13-18, Mar. 2003. (In Japanese)
↑

2002 †

  1. Satoshi Tayu and Mineo Kaneko, "Characterization and computation of stiner tree routing based on elmore's delay model," IEICE Trans. Fundamentals, Vol. E85-A, No. 12, pp. 2764-2774, Dec. 2002.
  2. Satoshi Tayu and Mineo Kaneko, "The width constrained placement by the simulated annealing with the sequence-pair encoding," Technical Report of IEICE (VLD2002-100), Vol. 102, No. 476, pp. 109-114, Nov. 2002.
  3. Satoshi Tayu and Mineo Kaneko, "Characterization and computation of stiner wiring based on elmore's delay model," Proc. Asia Pacific Conference on Circuits and Systems, Vol. 2, pp. 335-340, Oct. 2002.
  4. Yasuhiro Takashima, Akira Kaneko, Shinji Sato and Mineo Kaneko, "Two-dimensional placement method based on divide-and-replacement," Proc. Asia Pacific Conference on Circuits and Systems, Vol. 2, pp. 341-346, Oct. 2002.
  5. Koji Ohashi and Mineo Kaneko, "Heuristic assignment-driven scheduling for datapath synthesis," Proc. IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 703-706, May 2002.
  6. Mineo Kaneko, Jun'ichi Yokoyama and Satoshi Tayu, "3D scheduling based on code space exploration for dynamically reconfigurable systems," Proc. IEEE International Symposium on Circuits and Systems, Vol. V, pp. 465-468, May 2002.
  7. Satoshi Tayu, Takayuki Obata and Mineo Kaneko, "Efficient search on solution space based on sequence-pair for simulated annealing approach," Technical Report of IEICE (VLD2002-5), Vol. 102, No. 72, pp. 25-30, May 2002.
  8. Kasuaki Oshio and Mineo Kaneko, "Fault tolerant datapath based on algorithmic redundancy and voting," Techinical report of IEICE (VLD2002-11), Vol. 102, No. 73, pp. 19-24, May 2002.
  9. Toshiyuki Yorozuya, Koji Ohashi and Mineo Kaneko, "Assignment-driven loop pipeline scheduling and its application to data-path synthesis," IEICE Trans. Fundamentals, Vol. E85-A, No. 4, pp. 819-826, Apr. 2002.
  10. Koji Ohashi and Mineo Kaneko, "Minimization of iteration period in assignment-constrained schedule for datapath synthesis," Proc. 15th Workshop on Circuits and Systems in Karuizawa, pp. 441-446, Apr. 2002.
  11. Akira Kaneko, Yasuhiro Takashima, Shinji Sato and Mineo Kaneko, "2-dimensional placement method based on iterative divide-and-replacement," Technical Report of IEICE (VLD2001-146), Vol. 101, No. 694, pp. 1-8, Mar. 2002. (In Japanese)
↑

2001 †

  1. Mineo Kaneko, "Reliable data routing for spatial-temporal TMR multiprocessor systems," IEICE Trans. Information and Systems, Vol. E84-D, No. 12, pp. 1790-1800, Dec. 2001.
  2. Koji Ohashi and Mineo Kaneko, "Assignment-driven heuristic scheduling based on sensitivity to iteration period for datapath synthesis," Technical Report of IEICE, VLD2001-105, pp. 97-102, Nov. 2001.
  3. Mineo Kaneko and Yasuaki Maekawa, "Extended dimensional threshold filtering - a bridge between FIR filter and median type filter," Proc. IEEE International Symposium on Circuits and Systems, May 2001.
  4. Takayuki Hirama, Yasuhiro Takashima, Shinji Sato and Mineo Kaneko, "2D assignment optimization method based on simulated quenching," Technical Report of IEICE (VLD2000-135), Vol. 100, No. 646, pp. 7-12, Mar. 2001. (In Japanese)
  5. Toshiyuki Yorozuya, Koji Ohashi and Mineo Kaneko, "Assignment-driven pipeline scheduling and its application to data-path synthesis," Technical Report of IEICE (VLD2000-141), Vol. 100, No. 646, pp. 43-48 Mar. 2001. (In Japanese)
  6. Jun'ichi Yokoyama, Mineo Kaneko and Satoshi Tayu, "Packing based 3D scheduling for dynamically reconfigurable systems," Technical Report of IEICE (CAS2000-133), Vol. 100, No. 718, pp. 43-50, Mar. 2001. (In Japanese)
  7. Toshiyuki Yorozuya, Koji Ohashi and Mineo Kaneko, "Assignment-driven loop pipelining and its application to high level synthesis," Proc. Workshop on Synthesis and System Integration of Mixed Technology, Jan. 2001.
↑

2000 †

  1. Mineo Kaneko, Yuuichiro Shimizu and Satoshi Tayu, "Assignment-space exploration approach to testable data-path synthesis for minimizing partial scan registers," Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 540-543, Dec. 2000.
  2. Satoshi Tayu, Motoyasu Katsura and Mineo Kaneko, "An approximation algorithm for multiprocessor scheduling of trees with communication delays," Proc. International Symposium on Parallel Architectures, Algorithms, and Networks, pp. 114-120, Dec. 2000.
  3. Koji Ohashi, Mineo Kaneko and Satoshi Tayu, "Assignment-space exploration approach to concurrent data-path/floorplan synthesis," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors, pp. 370-375, Sep. 2000
  4. Choon-Sik Park and Mineo Kaneko, "An efficient scheme based on extended PDC graph model in synthesizing fault tolerant FIR filter," Proc. IEEE International Symposium on Circuits and Systems, Vol. 5, pp. 253-256, May 2000.
  5. Mineo Kaneko, Yoshikata Nishio and Satoshi Tayu, "Exact and heuristic methods of assignment driven scheduling for data-path synthesis applications," Proc. IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 57-60, May 2000.
  6. Koji Ohashi, Mineo Kaneko and Satoshi Tayu, "Assignment-driven approach to data-path synthesis incorporated with floorplanning," Technical Report of IEICE, (VLD99-117), Vol. 99, No. 658-661, pp. 1-8, Apr. 2000.
  7. Koji Ohashi, Mineo Kaneko and Satoshi Tayu, "Assignment-driven approach to data-path synthesis incorporated with floorplanning," Technical Report of IEICE (VLD99-117), Vol. 99, No. 659, pp. 1-8, Mar. 2000. (In Japanese)
  8. Hongdeuk Kim, Mineo Kaneko and Satoshi Tayu, "Graph planarization for floorplanning with considering global routing," Technical Report of IEICE (VLD99-121), Vol. 99, No. 659, pp. 33-40, Mar. 2000. (In Japanese)
  9. Mineo Kaneko and Yasuaki Maekawa, "Extended dimensional threshold filtering: a class on nonlinear filtering," Technical Report of IEICE (CAS99-111), Vol. 99, No. 552, pp. 1-8, Jan. 2000.
  10. Motoyasu Katsura, Satoshi Tayu and Mineo Kaneko, "An efficient scheduling of tasks with communication delays," Technical Report of IEICE (CAS99-118), Vol. 99, No. 552, pp. 55-62, Jan. 2000. (In Japanese)
↑

1999 †

  1. Choon-Sik Park and Mineo Kaneko, "Checking scheme for ABFT systems based on modified PD graph under an error generation/propagation model," IEICE Trans. Fundamentals, Vol. E82-A, No. 6, pp. 1002-1008, June 1999.
  2. Mineo Kaneko, "Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power," Proc. IEEE Internatinal Symposium on Circuits and Systems, pp. 262-265, May 1999.
  3. Tadao Kadodi, Satoshi Tayu and Mineo Kaneko, "Steiner routing based on Elmore delay model," Technical Report of IEICE (VLD98-135), Vol. 98, No. 624, pp. 27-34, Mar. 1999. (In Japanese)
  4. Yuichiro Shimizu and Mineo Kaneko, "Data path synthesis for minimizing scan registers," Technical Report of IEICE (VLD98-146), Vol. 98, No. 625, pp. 41-47, Mar. 1999. (In Japanese)
  5. Yoshitaka Nishio, Mineo Kaneko and Satoshi Tayu, "Assignment based approach to high level synthesis for net relevant design criteria," Technical Report of IEICE (VLD98-147), Vol. 98, No. 625, pp. 49-56, Mar. 1999.
↑

1998 †

  1. Mineo Kaneko, "Reconfiguration of folded torus PE networks for fault tolerant WSI implementations," Proc. IEEE Asia-Pacific Conference on Circuits and Systems, pp. 791-794, Nov. 1998.
  2. Choon-Sik Park and Mineo Kaneko, "Checking scheme for ABFT systems based on modified PD graph under an error generation/propagation model," Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1703-1706, July 1998.
  3. Fernando G. V. Resende, Paulo S. R. Diniz, Keiichi Tokuda, Mineo Kaneko and Akinori Nishihara, "New adaptive algorithms based on multi-band decomposition of the error signal," IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 45, No. 5, pp. 592-599, May 1998.
  4. Mineo Kaneko, "Scheduling and reliability aspects of data routing in triplicated TMR systolic/multi-processor systems," Proc. International Conference on Massively Parallel Computer Systems, Apr. 1998.
  5. Choon-Sik Park and Mineo Kaneko, "An efficient technique for design of ABFT systems based on modified PD graph," Proc. International Conference on Massively Parallel Computer Systems, Apr. 1998.
  6. Mineo Kaneko, "Scheduling and reliability aspects of data routing for fault tolerant systolic arrays," Technical Report of IEICE (VLD97-136), Vol. 97, No. 577, pp. 103-110, Mar. 1998.
  7. Hiroshi Murata, Kunihiko Fujiyoshi and Mineo Kaneko, "VLSI/PCB placement with obstacles based on sequence pair," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 1, pp. 60-68, Jan. 1998.
↑

1997 †

  1. Fernando G. V. Resende, Paulo S. R. Diniz, Keiichi Tokuda, Mineo Kaneko and Akinori Nishihara, "LMS－based algorithms with multi-band decomposition of the estimation error applied to system identification," IEICE Trans. on Fundamentals, Vol. E80-A, No. 8, pp. 1376-1383, Aug. 1997.
  2. Fernando G. V. Resende, Paulo S. R. Diniz, Keiichi Tokuda, Mineo Kaneko and Akinori Nishihara, "Multi-band decomposition of the linear prediction error applied to the least-mean-square method with fixed and variable step-sizes," '''Proc. International Symposium on Circuits and Systems, Vol. 4, pp. 2176-2179, June 1997.
  3. Mineo Kaneko and Choon-Sik Park, "Link Sharing for Reliable TMR Systolic Arrays," Technical Report of IEICE (CAS97-34), Vol. 97, No. 137, pp. 127-134, June 1997.
  4. Fernando G. V. Resende, Paulo S. R. Diniz, Mineo Kaneko and Akinori Nishihara, "Adaptive AR spectral estimation based on multi-band decomposition of the linear prediction error with variable forgetting factors," Proc. International Conference on Acoustics, Speech, and Signal Processing, pp. 2185-2188, Apr. 1997.
  5. Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko, "VLSI/PCB placement with obstacles based on sequence-pair," Proc. International Symposium on Physical Design, pp. 26-31, Apr. 1997.
  6. Tsumagari Yasufumi and, Mineo Kaneko, "---," Technical Report of IEICE (VLD96-92), Vol. 96, No. 555, pp. 41-48, Mar. 1997. (In Japanese)
  7. Kunihiro Fujiyoshi, Takeshi Miwa, Hiroshi Murata, Mineo Kaneko, "Area minimization for module placement including a novel type of soft-module," Technical Report of IEICE (VLD96-104), Vol. 96, No. 555, pp. 63-70, Mar. 1997. (In Japanese)
  8. Fernando G. V. Resende, Keiichi Tokuda, Mineo Kaneko and Akinori Nishihara, "Multi-band decomosition of the linear prediction error applied to adaptive AR spectral estimation," IEICE Trans. on Fundamentals, Vol. E80-A, No. 2, pp. 365-376, Feb. 1997.
  9. Mineo Kaneko and Jialin Tian, "Concurrent cell generation and mapping for CMOS logic circuits," Proc. Asia and South Pacific Design Automation Conference, pp. 247-252, Jan. 1997.
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1996 †

  1. Mineo Kaneko and Hiroyuki Miyauchi, "A systematic design of fault tolerant systolic arrays based on triple modular redundancy in time-processor space," IEICE Trans. on Information and Systems, Vol. E79-D, No. 12,pp. 1676-1689, Dec. 1996. (In Japanese)
  2. Taiichi Hamano, Keiichi Tokuda and Mineo Kaneko, "Image restoration based on estimation of fractal structure," Proc. of TENCON, pp. 311-316, Nov. 1996.
  3. Fernando G. V. Resende, Keiichi Tokuda, Mineo Kaneko and Akinori Nishihara, "RLS algorithms for adaptive AR spectrum analysis based on multi-band decomposition of the linear prediction error," Proc. of TENCON, pp. 541-546, Nov. 1996.
  4. Mineo Kaneko, Hiroyuki Miyauchi and Choon-Sik Park, "Link sharing scheme for fault tolerant systolic arrays based on mixed spatial - temporal triple modular redundancy," Proc. IEEE Asia-Pacific Conference on Circuits and Systems, pp. 472-475, Nov. 1996.
  5. Fernand G. V. Resende, Paulo S. R. Diniz, Keiichi Tokuda, Mineo Kaneko and Akinori Nishihara, "LMS-based algorithms with multi-band decomposition of the linear prediction error," Proc. of IEICE 11th DSP Symposium, pp. 379-384, Nov. 1996.
  6. Fernando G. V. Resende, Keiichi Tokuda and Mineo Kaneko, "Adaptive AR spectrum estimation based on wavelet decomposition of the linear prediction error," IEICE Trans. on Fundamentals, Vol. E79-A, No. 5, pp. 665-673, May 1996.
Kaneko Lab. | School of Information Science | JAIST
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