Themes

Circuit theory and CAD for VLSIs †

VLSI is a collection of a huge number of transistors and interconnections between them, and its design is to find one or some configurations which satisfy specifications in the functional behavior. Various kinds of performances associated with each configuration, such as area, speed, power and testability, are necessary also to be optimized. Hierarchical design is inevitably introduced to transform the problem to be computationally manageable. Hence, besides optimization algorithms, the design model for each abstract level, by which the final VLSI performance can be well estimated/controlled and at the same time the problem size can be reduced to be a manageable level, is also a key for successful CAD for VLSIs. High level synthesis for application specific embedded VLSIs is one of our major interests. Our challenge includes high level synthesis for extremely high performance VLSIs considering post-silicon tuning, integrated formulation of whole tasks in high level synthesis and its solution for deeply optimized VLSIs, etc.

Fault tolerant VLSI computing †

Parallelism and pipelining together with the well structured multiple processing elements are promising solutions to various computation problems in the field. Fault-tolerance and dependability as well will become the important functions for WSI/VLSI systems. Multiple modular redundancy in mixed spatial-temporal space, algorithm based fault tolerance, reconfiguration and unified theory of these techniques are studied with emphasis on WSI/VLSI computation. We are also interested in High-level synthesis for application specified fault tolerant VLSI systems and related design theory and algorithms.

VLSI signal processing †

The evolution in VLSI technology allows various complicated and computationally intensive algorithms to be implemented on VLSI chip. Performance measures for such VLSI computation include function and performance of a computation algorithm itself, area (hardware cost), computation time, throughput rate, accuracy (finite word length effects), power, etc. We are trying to find solutions through an approach of the algorithm/software/hardware co-design. Modularity and regularity analysis of numerical computation algorithms, algorithm transformation and optimization and interaction between algorithm transformation and software/hardware co-design are the central interests of ours.

VLSI testing †

According to the ITRS (International Technology Roadmap for Semiconductors) 2001, it is expected that the percentage of the cost of testing VLSI circuits becomes higher as the size and speed of the circuits increase. In order to overcome this problem, breakthroughs in test technologies are needed. We are investigating test technologies to perform testing efficiently, e.g., test generation, design for testability, synthesis for testability, etc.