Yasushi Inoguchi Professor
School of Information Science、Security and Networks Area
B.E. degree from Tohoku University(1991), M.S. degree from JAIST(1994), Ph.D. degree from JAIST(1997)
2008/4/1-2009/3/31University of South FloridaCourtesy Senior Research Scholar
Massively Parallel Computers, Interconnection of Multi-processor Systems, Fault-Tolerant and Thermal Analysis of WSI stacks.
Massively Parallel, Computer Architecture, Reconfigurable System, e-Learning
Interconnection networks for Massively Parallel Computer
Multiprocessor systems consisting of millions of processing elements have been expected to solve advanced scientific and engineering problems in the next decade. Since the interconnection network is one of the critical components of multiprocessor systems, they are required network feature such as smaller diameter, easy VLSI implementation, fault-tolerant schemes, and good expandability. We are studying hierarchical interconnection network named as Shifted Recursive Torus (SRT) for scientific computing, and discuss network performance, routing algorithms, and fault-tolerant schemes.
Cooling Schemes for 3D Stacked Implementation
For 3D Stacked Implementation systems, cooling is one of the most crucial problems to implement massively parallel systems. On the other hand, the reconfiguration to avoid defects on wafers is also important for wafer scale integration systems and some unused processing elements (PEs) are remained as a result of reconfiguration. Since operative PEs generate heavy heat but unused PEs generate no heat, we can cool the stacks replacing these PEs. We are studying reconfiguration algorithms for Shifted Recursive Torus (SRT) network in 3D stacked implementation by considering thermo-radiation in stacked wafers implementation. We discuss cooling schemes for SRT networks to keep highly cooling network performance in stacked wafers implementation. Cooling approaches have been proposed for SRT in stacked implementation. Introducing a thermo-radiation model into SRT in stacked implementation, cooling and reconfiguration performance of SRT is evaluated.
Multi-port Memory Computer Architectures
It is important for multiprocessor systems to increase communication speed between processing elements. We discuss a hypercube multiprocessor based on a multiport memory which is able to reduce the communication overhead. A prototype multiprocessor system is constructed to evaluate the communication performance of a multiport memory scheme. It is confirmed that high communication performance is realized by prototype system consisting of multiport memory.
Ultra fine grained parallel processing by hard ware programming
Logical circuits on a VLSI chip operate in parallel essentially because sub-circuits on the chip execute their functions independently. Thus, ultra fine grade parallel processing can be achieved if operators in a software algorithm can be spread as parallel arithmetic circuits on these VLSI chips.In this research, a scheme is examined that extract operator level parallelism from a software algorithm, compile them to hardware description language, and implement the algorithm as parallel arithmetic units on hardware circuits directly.
- Computational Science and Its Applications -- ICCSA 2013, Lecture Notes in Computer Science, Hierarchical Tori Connected Mesh Network，M.M. Hafizur Rahman, Asadullah Shah, Masaru Fukushi and Yasushi Inoguchi，Springer-Verlag Berlin Heidelberg，2013，197-210
- , Hierarchical Interconnection Networks for Massively Parallel Computer Systems，M.M. Hafizur Rahman and Yasushi Inoguchi，LAMBERT，2011
- Lecture Notes in Computer Science, Session 6A: Grid Scheduling and Algorithms II, Dynamic Task Scheduling Algorithm for Grid Computing System，Yuanyuan Zhang, Yasushi Inoguchi and Hong Shen，Springer，2005，578-583
- Probabilistic Strategies Based on Staged LSH for Speedup of Audio Fingerprint Searching with Ten Million Scale Database，Masahiro Fukuda and Yasushi Inoguchi，International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)， 6 pages in CD-ROM，June 7, 2017
- A new power efficient high performance interconnection network for many-core processors，Faiz Al Faisal, M.M. Hafizur Rahmana and Yasushi Inoguchi，Journal of Parallel and Distributed Computing, Elsevier，101， 92-102，Mar., 2017
- A compression method for storage formats of sparse matrix in solving the large scale linear systems，Tomoki Kawamura, Yoneda Kazunori, Takashi Yamazaki, Takashi Iwamura, Masahiro Watanabe and Yasushi Inoguchi，In 19th Workshop on Advances in Parallel and Distributed Computational Models (APDCM) held in conjunction with 31rd IEEE International Parallel and Distributed Processing Symposium (IPDPS)， 924-931，Mar. 29, 2017
◇Lectures and Presentations
- Probabilistic Strategies Based on Staged LSH for Speedup of Audio Fingerprint Searching with Ten Million Scale Database，Masahiro Fukuda and Yasushi Inoguchi，International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)，Bochum, DE，June 7, 2017
- A compression method for storage formats of sparse matrix in solving the large scale linear systems，Tomoki Kawamura, Yoneda Kazunori, Takashi Yamazaki, Takashi Iwamura, Masahiro Watanabe and Yasushi Inoguchi，In 19th Workshop on Advances in Parallel and Distributed Computational Models (APDCM) held in conjunction with 31rd IEEE International Parallel and Distributed Processing Symposium (IPDPS)，Orlando, FL, USA，Mar. 29, 2017
- Power Analysis with Variable Traffic Loads for Next Generation Interconnection Networks，Faiz Al Faisal, M.M. Hafizur Rahman and Yasushi Inoguchi，18th IEEE International Conference on High Performance Computing and Communications (HPCC 2016)，Sydney, Australia，Dec. 12-14, 2016
◇Academic Society Affiliations
- IEICE，Editor，IEICE TRANSACTIONS on Info. and Sys., E96-D, Special Section on Reconfigurable Systems，2012-2013
- Fukui University，2017/09/07 - 2017/09/27
- SC16 (International Conference for High Performance Computing, Networking, Storage and Analysis)，2016/11/14 - 2016/11/17