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2021
- Yinglin, YU, Fault Tolerant FPGA Supporting Online Error Correction and Fault Repairing (Master thesis)
- Yu, SHA, Optimization of Register Transfer Level Datapath Circuit Considering Temperature-Dependent Delays (Master thesis)
2020
- Jun NIU, High Performance Multiply-Accumulate Unit Bases on Wallace Tree and Parallel Prefix Adder (Master thesis)
- Tomohiro NOGUCHI, 3D Floorplan Optimization considering 3D Soft Modules (Master thesis)
2019
- Junghoon OH, Temporal and Spatial Redundancy Optimization for Efficient Fault-Tolerant LSIs (Doctoral thesis)
2018
- Hindawi Omran, Coding and Optimization of Three-Dimensional Module Placement for Three-Dimensional Stacked LSI (Master thesis)
2017
- Tatsuhiro NISHIOKA, Optimized Design of Parallel Prefix Adder Considering Buffer Insertion (Master thesis)
- Cheng MA, Reconfiguration for Fault Tolerant FPGA Considering Incremental Multiple Faults (Master thesis)
2016
- Xiaogung LI, Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High Level Synthesis (Master thesis)
- Kai SHIMURA, A Complete MILP Formulation of Skew-Aware High Level Synthesis (Master thesis)
- Makoto SOGA, Optimization of Temperature Dependent Intentional Skew for Temperature Aware Timing Design (Master thesis)
- Takayuki MOTO, Design of Low-Power Parallel Prefix Adders in Consideration of Input Switching Activity (Master thesis)
2015
- Kazuho KATSUMATA, Resource Binding in Datapath Synthesis for Performance Enhancement by Post-Silicon Skew Tuning (Master thesis)
2014
2013
- Junghoon Oh, High Area-Efficient Soft-Error Tolerant Datapath Design (Master thesis)
- Koutaro KATO, A Design Method of Mixed Synchronous-Asynchronous Circuits (Master thesis)
- Tatsunori KUBO, Post Silicon Tuning of Body Biasing and Clock Skew for Low-Voltage LSI (Master thesis)
2012
2011
- Yosuke HARUTA, Resource Binding for High Performance LSI for Enhanced Post-Silicon Skew Tunability (Master thesis)
- Jian LI, An Algorithms for Post-Silicon Skew Tuning Based on Iterative Path Delay Testing (Master thesis)
2010
- Syuichi SOWA, Low Power Design of Digital Circuits using Quasi-Complementary MOS Gates (Master thesis)
- Yu DANG, Delay Variation-Aware Datapath Synthesis for Skew Adjustability (Master thesis)
2009
- Keisuke INOUE, Constraint-Based Approaches and Optimizations to Variability-Tolerant Datapath Synthesis (Doctoral thesis)
- Madoka SATO, Optimization of Graph Embedding Based on Pattern-Embedding and Relevant Operations (Master thesis)
- Eiri TAKEDA, A Test Scheduling Method for Asynchronous Interconnects Based on Cone Partitioning (Master thesis)
- Akira TEHARA, High-Level Design Conditions and Techniques for Post-Fabrication Timing-Adjustable Datapaths (Master thesis)
2008
- Takayuki OBATA, Advanced Datapath Synthesis Incorporating Intentional Timing Skew for High Performance Nanometer VLSIs (Doctoral thesis)
- Yayumi UEHARA, A Tunable LSI Based on Timing Skew and Stall Adjustments (Master thesis)
- Yutaka TSUBOISHI, Fault Tolerant Datapath Synthesis Starting with Triple Algorithm Redundancy (Master thesis)
2007
- A code system and optimization for rectangle packing in 2D torus space (Takayuki Shibata, Master's Thesis)
- Test generation for dual-rail two-phase circuits based on time expansion of C-elements (Masaaki Takegahara, Master's Thesis)
2006
- Structural delay-variation tolerance and high level synthesis
for datapaths (Keisuke Inoue, Master's Thesis)
- Model placement using wire length aware partially ordered Sequence-Pair (Yuki Yano, Master's Thesis)
2004
- Auxiliary objective function approach to simulated annealing based rectangle packing (Shinichi Ogawa, Master's Thesis)
- A finite solution space for recurrent placements of rectangles (Tomoyuki Ogawa, Master's Thesis)
2003
- Optimaization in higher abstraction level design for high performance VLSI systems (Yuta Kiyasu, Master's Thesis)
2002
- Assignment-centric approach to data-path synthesis for application specific VLSIs (Koji Ohashi, Doctoral Thesis)
- Regularity extraction from computation algorithm and its application to data-path synthesis (Yoshihiko Atsumi, Master's Thesis)
- Floorplan synthesis with rearrangement of hierarchical structure (Masahiro Obara, Master's Thesis)
- Optimization of register to register data transfer for high level synthesis (Takayuki Obata, Master's Thesis)
A systematic design method of quasi-systolic arrays (Seiichi Sugimoto, Master's Thesis)
- Assignment-driven module selection and scheduling for data-path synthesis (Masaaki Yasuda, Master's Thesis)
2001
- 2-dimensional placement method based on divide-and-replacement (Akira Kaneko, Master's Thesis)
- Synthesis of fault tolerant datapath based on triple algorithm redundancy (Kazuaki Oshio, Master's Thesis)
2000
- Two-dimensional cell assignment optimazation based on simulated quenching (Takayuki Hirama, Master's Thesis)
- Packing based 3D scheduling for dynamically reconfigurable system (Junichi Yokoyama, Master's Thesis)
- Assignment-driven pipeline scheduling and its application to data-path synthesis (Toshiyuki Yorozuya, Master's Thesis)
1999
- Algorithm-based fault tolerant systems based on graph-theoretic error occurrence/propagation models (Choon-Sik Park, Doctoral Thesis)
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